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LM1771 Datasheet(PDF) 10 Page - Texas Instruments |
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LM1771 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 26 page VOUT + VDS_NMOS D = VIN + VDS_NMOS + VDS_PMOS VOUT D = VIN LM1771 SNVS446C – JUNE 2006 – REVISED APRIL 2013 www.ti.com Soft-Start To limit in-rush current and allow for a controlled startup the LM1771 incorporates an internal soft-start scheme. Every time the enable voltage rises rises above 1.2V while VIN is greater than the UVLO threshold, the LM1771 goes through an adaptive soft-start that limits the on-time and expands the minimum off-time. In addition the part will only activate the PMOS allowing a discontinuous mode of operation enabling a pre-biased startup. The time spent in soft-start will depend on the load applied to the output, but is usually close to a set time that is dependent on the timing option. The approximate soft-start time can be seen below for each timing option. Product ID Timing TSS LM1771S 0.5 µs 1 ms LM1771T 1.0 µs 1.2 ms LM1771U 2.0 µs 1.8 ms It should be noted that as soon as soft-start terminates the short-circuit protection is enabled. This means that if the output voltage does not reach at least 68% of its final value the part will latch off. Therefore, if the input supply is extremely slow rising such that at the end of soft-start the input voltage is still near the UVLO threshold, a timing option should be chosen to ensure that maximum duty-cycle permits the output to meet the minimum condition. As a general recommendation it is advisable to use the 2000 ns option (LM1771U) in conditions where the output voltage is 2.5V or greater to avoid false latch offs when there is concern regarding the input supply slew rate. In some situations, the internal soft-start routine can create a slight overshoot on the output voltage. If this must be avoided, the use of a feed-forward capacitor as detailed in the Feed-Forward Capacitor section of this datasheet is recommended. Jitter The LM1771 utilizes an adaptive on-time control scheme that relies on the output voltage ripple to provide a consistent switching frequency. Under certain conditions, excessive noise can couple onto the feedback pin causing the switch node to appear to have a slight amount of jitter. This is not indicative of an unstable design. The output voltage will still regulate to the exact same value. Careful component selection and layout should minimize any external influence. In addition to any external noise that can add to the jitter seen on the switch node, the LM1771 will always have a slight amount of switch jitter. This is because the LM1771 makes a small alteration in the reference voltage every 128 cycles to improve its accuracy and long term performance. This has the effect of causing a change in the switching frequency at that instant. When viewed on an oscilloscope this can be seen as a jitter in the switch node. The change in feedback voltage or output voltage, however, is almost indistinguishable. DESIGN GUIDE The following section walks the designer through the steps necessary to select the external components to build a fully functional power supply. As with any DC-DC converter numerous trade-offs are possible to optimize the design for efficiency, size or performance. These will be taken into account and highlighted throughout this discussion. The first equation to calculate for any buck converter is duty-cycle. Ignoring conduction losses associated with the FETs and parasitic resistances it can be approximated by: (7) A more accurate calculation for duty-cycle can be used that takes into account the voltage drops across the FETs. This equation can be used to determine the slight load dependency on switch frequency if needed. Otherwise the simplified equation works well for component calculation. (8) 10 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM1771 |
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