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LM3754 Datasheet(PDF) 3 Page - Texas Instruments |
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LM3754 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 47 page LM3754 www.ti.com SNVS789B – JANUARY 2012 – REVISED APRIL 2013 Pin Descriptions (continued) Pin Number Pin Name Description 12 SYNC Synchronization Input. SYNCOUT of one controller is connected to SYNC of the next controller in a daisy-chain fashion. To synchronize the whole chain of controllers to an external clock, wire the external clock to the SYNC pin of the first controller of the chain (called the Master controller). Otherwise, connect the SYNC input of the Master controller to ground and all of the controllers will be controlled by the internal oscillator of the Master. 13 FAULT Input/Output. Wire the FAULT pin of all controllers together. FAULT gets pulled Low during startup, an over-current fault, or an over-voltage fault. FAULT = Low signals all controllers to stop switching and prepare for the next startup sequence. The first LM3754 in the system (the Master) supplies the FAULT pin pull-up current for all of the controllers. 14 NBASE Connect to the base of external series-pass NPN if using the LM3754 internal LDO controller to generate VDD. Otherwise leave unconnected. 15 VIN Input Voltage. Connect VIN to the input supply rail used to supply the power stages. This input is used to provide the feed-forward for the voltage control of VOUT and for generating the internal VCC voltage. 16 VCC Supply for internal control circuitry. Decouple VCC to PGND with a ceramic capacitor. When VIN > 5.5V, the internal LDO will supply 4.35V to this pin. When 4.5V < VIN < 5.5V, connect VIN to VCC. In this case the internal VCC LDO will turn off and VCC current will be supplied directly by VIN. 17 SGND Signal Ground. Tie PGND and SGND together on the board through the DAP. 18 COMP Error Amplifier Output. For the Master, a compensation network is placed between the COMP pin and the FB pin. The COMP pin of the Master should be connected to the SNSP pin of each of the Slaves. The COMP pin of each of the Slaves must be connected to its VDIF pin 19 FB Feedback Input. This is the inverting input of the error amplifier. Connect the Master FB pin to the output voltage divider and compensation network. Connect each Slave FB pin to its own VCC pin. This will put that controller in Slave mode and disable its error amplifier. 20 VDIF Output of the remote-sense differential amplifier. Connect the Master VDIF pin to the output voltage divider and compensation network. The Slave differential amplifier is used to buffer COMP from the Master controller. Connect each Slave VDIF pin to its own COMP pin. 21 SNSM Inverting input of the remote-sense differential amplifier. Connect SNSM of the Master controller to PGND at the load point. On Slave controllers, the differential amplifier is used to buffer COMP from the Master controller. Connect SNSM of each Slave controller directly to the Master controller SGND pin. 22 SNSP Non-inverting input of the remote-sense differential amplifier. Connect the SNSP of the Master controller to VOUT at the load point. On Slave controllers, the differential amplifier is used to buffer COMP of the Master controller. Connect SNSP of each Slave controller to the Master controller COMP pin. 23 SS Soft-Start. Connect the SS pins of all of the controllers in the system together. At the Master controller, connect a soft-start capacitor between SS and SGND. Only the Master controller supplies the pull up current to the SS capacitor. 24 FREQ Frequency Adjust. A frequency adjust resistor and decoupling capacitor are connected between FREQ and SGND to program the switching frequency between 200 kHz to 1 MHz (each phase). These components must be supplied on the Master and Slaves, even if the system is synchronized to an external clock. 25 IAVE Current Averaging. Connect a 4.02 k Ω, 1%, resistor between each controller’s IAVE pin and SGND. In the case where one phase is not used, connect an 8.06 k Ω resistor. Connect a filter capacitor between IAVE and SGND at each controller, 26 EN Enable Input. Used for VIN UVLO function, connect EN to the midpoint of a voltage divider from VIN to SGND. The EN pins of all controllers must be wired together. For an on/off EN function, wire the EN pins of all controllers together and control with an open drain output. 27 CS2 Positive current-sense input of Phase 2. Connect to the DCR network or the current-sense resistor of Phase 2. The negative current-sense input is the CSM pin. 28 ILIM Current Limit Set. Connect a resistor between ILIM and CSM. The resistance between ILIM and CSM programs the current limit. 29 CSM Negative current-sense input of the internal current-sense amplifiers. Connect to VOUT. 30 CS1 Positive current-sense input of Phase 1. Connect to the DCR network or the current-sense resistor of Phase 1. The negative current-sense input is the CSM pin. 31 PH Phase Select Input. Connect this pin to the middle of a resistor divider between VCC and SGND to program the number of phases in the system. 32 BOOT2 Bootstrap pin of Phase 2 for the high-side gate drive power supply. DAP Die Attach Pad. Must be connected to PGND and SGND but cannot be used as the primary ground connection; do not place any traces or vias other than GND in the outer layer under the DAP; see application note AN-1187 (literature number SNOA401). Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM3754 |
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