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TC7662BEOA Datasheet(PDF) 4 Page - Microchip Technology |
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TC7662BEOA Datasheet(HTML) 4 Page - Microchip Technology |
4 / 11 page 4 TC7662B CHARGE PUMP DC-TO-DC VOLTAGE CONVERTER TC7662B-8 9/11/96 © 2001 Microchip Technology Inc. DS21469A 4. When using polarized capacitors in the inverting mode, the + terminal of C1 must be connected to pin 2 of the TC7662B and the – terminal of C2 must be connected to GND. 5. If the voltage supply driving the TC7662B has a large source impedance (25-30 ohms), then a 2.2 µF capaci- tor from pin 8 to ground may be required to limit the rate of rise of the input voltage to less than 2V/ µsec. TYPICAL APPLICATIONS Simple Negative Voltage Converter The majority of applications will undoubtedly utilize the TC7662B for generation of negative supply voltages. Figure 3 shows typical connections to provide a negative supply where a positive supply of +1.5V to +15V is available. Keep in mind that pin 6 (LV) is tied to the supply negative (GND) for supply voltages below 3.5 volts. a. b. The output characteristics of the circuit in Figure 3 can be approximated by an ideal voltage source in series with a resistance as shown in Figure 3b. The voltage source has a value of–(V+). The output impedance (RO) is a function of the ON resistance of the internal MOS switches (shown in Figure 2), the switching frequency, the value of C1 and C2, and the ESR (equivalent series resistance) of C1 and C2. A good first order approximation for RO is: RO ≅ 2(RSW1 + RSW3 + ESRC1) + 2(RSW2 + RSW4 + ESRC1) + + ESRC2 (fPUMP = , RSWX = MOSFET switch resistance) Combining the four RSWX terms as RSW, we see that: RO ≅ 2 x RSW + + 4 x ESRC1 + ESRC2Ω RSW, the total switch resistance, is a function of supply 1 fPUMP x C1 fOSC 2 1 fPUMP x C1 t2 t1 B A V –(V+) 0 Figure 4. Output Ripple Figure 3. Simple Negative Converter and its Output Equivalent 1 2 3 4 8 7 6 5 TC7662B 10 µF + V+ + 10 µF VOUT = –V+ – – VOUT RO V+ + – 1 2 x fPUMP x C2 1 (5 x 103 x 10 x 10-6) voltage and temperature (See the Output Source Resis- tance graphs), typically 23 Ω at +25°C and 5V. Careful selection of C1 and C2 will reduce the remaining terms, minimizing the output impedance. High value capacitors will reduce the 1/(fPUMP x C1) component, and low ESR capaci- tors will lower the ESR term. Increasing the oscillator fre- quency will reduce the 1/(fPUMP x C1) term, but may have the side effect of a net increase in output impedance when C1 > 10 µF and there is not enough time to fully charge the capacitors every cycle. In a typical application when fOSC = 10kHz and C = C1 = C2 = 10µF: RO ≅ 2 x 23 + + 4 x ESRC1 + ESRC2 RO ≅ (46 + 20 + 5 x ESRC) Ω Since the ESRs of the capacitors are reflected in the output impedance multiplied by a factor of 5, a high value could potentially swamp out a low 1/(fPUMP x C1) term, rendering an increase in switching frequency or filter capaci- tance ineffective. Typical electrolytic capacitors may have ESRs as high as 10 Ω. Output Ripple ESR also affects the ripple voltage seen at the output. The total ripple is determined by 2 voltages, A and B, as shown in Figure 4. Segment A is the voltage drop across the ESR of C2 at the instant it goes from being charged by C1 (current flowing into C2) to being discharged through the load (current flowing out of C2). The magnitude of this current change is 2 x IOUT, hence the total drop is 2 x IOUT x ESRC2 volts. Segment B is the voltage change across C2 during time t2, the half of the cycle when C2 supplies current to the load. The drop at B is IOUT x t2/C2 volts. The peak-to- peak ripple voltage is the sum of these voltage drops: VRIPPLE ≅ ( + ESRC2 x IOUT ) |
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