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LM25118 Datasheet(PDF) 4 Page - Texas Instruments

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No. de pieza LM25118
Descripción Electrónicos  LM25118, LM25118-Q1 Wide Voltage Range Buck-Boost Controller
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI - Texas Instruments

LM25118 Datasheet(HTML) 4 Page - Texas Instruments

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background image
RT
RAMP
AGND
SS
HS
VCC
LO
PGND
EN
FB
COMP
VOUT
VIN
UVLO
HO
HB
VCCX
CSG
CS
SYNC
1
2
3
4
8
7
6
5
9
10
11
12
13
14
15
16
17
18
19
20
Exposed Pad
on Bottom
(DAP)
LM25118, LM25118-Q1
SNVS726D – JULY 2011 – REVISED AUGUST 2014
www.ti.com
5 Pin Configuration and Functions
20 Pin HTSSOP with Exposed Pad
PWP Package
(Top View)
Pin Functions
PIN
DESCRIPTION
NUMBER
NAME
1
VIN
Input supply voltage.
If the UVLO pin is below 1.23 V, the regulator will be in standby mode (VCC regulator running, switching regulator
disabled). When the UVLO pin exceeds 1.23 V, the regulator enters the normal operating mode. An external
2
UVLO
voltage divider can be used to set an under-voltage shutdown threshold. A fixed 5 µA current is sourced out of the
UVLO pin. If a current limit condition exists for 256 consecutive switching cycles, an internal switch pulls the UVLO
pin to ground and then releases.
The internal oscillator frequency is set with a single resistor between this pin and the AGND pin. The recommended
3
RT
frequency range is 50 kHz to 500 kHz.
If the EN pin is below 0.5 V, the regulator will be in a low power state drawing less than 10 µA from VIN. EN must
4
EN
be raised above 3 V for normal operation.
Ramp control signal. An external capacitor connected between this pin and the AGND pin sets the ramp slope used
5
RAMP
for emulated current mode control.
6
AGND
Analog ground.
Soft-Start. An external capacitor and an internal 10 µA current source set the rise time of the error amp reference.
7
SS
The SS pin is held low when VCC is less than the VCC under-voltage threshold (< 3.7 V), when the UVLO pin is
low (< 1.23 V), when EN is low (< 0.5 V) or when thermal shutdown is active.
8
FB
Feedback signal from the regulated output. Connect to the inverting input of the internal error amplifier.
Output of the internal error amplifier. The loop compensation network should be connected between COMP and the
9
COMP
FB pin.
10
VOUT
Output voltage monitor for emulated current mode control. Connect this pin directly to the regulated output.
11
SYNC
Sync input for switching regulator synchronization to an external clock.
12
CS
Current sense input. Connect to the diode side of the current sense resistor.
13
CSG
Current sense ground input. Connect to the ground side of the current sense resistor.
14
PGND
Power Ground.
15
LO
Boost MOSFET gate drive output. Connect to the gate of the external boost MOSFET.
Output of the bias regulator. Locally decouple to PGND using a low ESR/ESL capacitor located as close to the
16
VCC
controller as possible.
Optional input for an externally supplied bias supply. If the voltage at the VCCX pin is greater than 3.9 V, the
17
VCCX
internal VCC regulator is disabled and the VCC pin is internally connected to VCCX pin supply. If VCCX is not
used, connect to AGND.
4
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Product Folder Links: LM25118 LM25118-Q1


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