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TPS40400 Datasheet(PDF) 4 Page - Texas Instruments |
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TPS40400 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 82 page TPS40400 SLUS930C – APRIL 2011 – REVISED OCTOBER 2015 www.ti.com Pin Functions (continued) PIN I/O(1) DESCRIPTION NAME NO. Power good output. This is an open-drain output that pulls low when any fault condition exists within the PGOOD 3 O device or when the device is not operating within a user-selectable operating range of the nominal output voltage of the converter. Signal ground for the device. Connect the ground of signal level circuits to this pin. Connections should SGND PAD – be arranged so that power level currents do not flow in the pad attached to the thermal plane or in the SGND portion of the circuit. SMBALRT 23 O Output used to signal that PMBus host that the device needs attention. This is the common connection for the flying high-side MOSFET driver and also serve as a sense line SW 17 I for the adaptive anti-cross-conduction circuitry Logic level input to the oscillator inside the device. The oscillator resets on the rising edge of a pulse SYNC 4 I train applied to this pin and begin a new switching cycle. Analog input to the noninverting side of the control loop error amplifier. The error amplifier has three inputs (voltage reference, TRACK and soft-start time) to its + side, and the lowest voltage applied to TRACK 5 I these three inputs dominate and control the output voltage of the whole converter. This pin is to allow the user to configure a voltage divider that allows the device output follow an external reference voltage during start-up. VDD 20 I Input power connection for the device. This pin requires a supply voltage of between 3 V to 20 V. VSNS+ 9 I Noninverting input to the unity gain remote voltage sense amplifier. VSNS– 10 I Inverting input to the unity gain remote voltage sense amplifier. 6 Specifications 6.1 Absolute Maximum Ratings (1) MIN MAX UNIT VDD –0.3 22 SW –5 27 BOOT –0.3 30 BOOT-SW, HDRV-SW (Differential from BOOT or HDRV to SW) –0.3 7 Input voltage V VSNS+, TRACK, SYNC, FB –0.3 7 DATA, CLK, CNTL –0.3 3.6 ISNS+, ISNS– –0.3 15 VSNS– –0.3 0.3 HDRV –0.3 30 BP3 –0.3 3.8 Output voltage V BP6, COMP, PGOOD, DIFFO, LDRV –0.3 7 SMBALRT, ADDR0, ADDR1 –0.3 3.6 Operating junction temperature, TJ –40 150 °C Storage Temperature, Tstg –55 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE UNIT Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V(ESD) Electrostatic discharge V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 4 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: TPS40400 |
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