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TPS54612 Datasheet(PDF) 10 Page - Texas Instruments |
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TPS54612 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 28 page (SS) (SS) 0.7 V t C 5 A = ´ m d (SS) 1.2 V t C 5 A = ´ m TPS54611, TPS54612, TPS54613 TPS54614, TPS54615, TPS54616 SLVS400D – AUGUST 2001 – REVISED JANUARY 2015 www.ti.com Feature Description (continued) 7.3.2 Slow-Start and Enable (SS/ENA) The slow-start/enable pin provides two functions. First, the pin acts as an enable (shutdown) control by keeping the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 V. When SS/ENA exceeds the enable threshold, device start up begins. The reference voltage fed to the error amplifier is linearly ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in approximately 3.35 ms. Voltage hysteresis and a 2.5-µs falling edge deglitch circuit reduce the likelihood of triggering the enable due to noise. Refer to Table 1 for startup times for each device. Table 1. Device Startup Times DEVICE OUTPUT VOLTAGE SLOW-START TPS54611 0.9 V 3.3 ms TPS54612 1.2 V 4.5 ms TPS54613 1.5 V 5.6 ms TPS54614 1.8 V 3.3 ms TPS54615 2.5 V 4.7 ms TPS54616 3.3 V 6.1 ms The second function of the SS/ENA pin provides an external means for extending the slow-start time with a ceramic capacitor connected between SS/ENA and AGND. Adding a capacitor to the SS/ENA pin has two effects on start-up. First, a delay occurs between release of the SS/ENA pin and start-up of the output. The delay is proportional to the slow-start capacitor value and lasts until the SS/ENA pin reaches the enable threshold. The start-up delay is approximately: (1) Second, as the output becomes active, a brief ramp up at the internal slow-start rate may be observed before the externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start capacitor. The slow-start time set by the capacitor is approximately: (2) The actual slow-start time is likely to be less than the above approximation due to the brief ramp up at the internal rate 7.3.3 VBIAS Regulator The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over temperature. The bypass capacitor should be placed close to the VBIAS pin and returned to AGND. External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.7 V, and external loads on VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be useful as a reference voltage for external circuits. 7.3.4 Voltage Reference The voltage reference system produces a precise, temperature-stable voltage from a bandgap circuit. A scaling amplifier and DAC are then used to produce the reference voltages for each of the fixed output devices. 7.3.5 Oscillator and PWM Ramp The oscillator frequency can be set to internally fixed values of 350 kHz or 550 kHz using the FSEL pin as a static digital input. If a different frequency of operation is required for the application, the oscillator frequency can be externally adjusted from 280 kHz to 700 kHz by connecting a resistor from the RT pin to AGND and floating the FSEL pin. The switching frequency is approximated by the following equation, where R is the resistance from RT to AGND 10 Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: TPS54611 TPS54612 TPS54613 TPS54614 TPS54615 TPS54616 |
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