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TPS65279VDAPR Datasheet(PDF) 11 Page - Texas Instruments |
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TPS65279VDAPR Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 46 page  TPS65279V www.ti.com SLVSBW1B – FEBRUARY 2013 – REVISED JANUARY 2014 ELECTRICAL CHARACTERISTICS (continued) TJ = 25°C, VIN = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BUCK 1, BUCK 2 CONVERTERS Vref(min) Voltage reference 0 A < IOUT1,2 < 5 A 0.594 0.6 0.606 V Output voltage step size VOUT1,2 8 10 12 mV (VID 0x00 – 0x7F) VLINEREG3 Line regulation-DC IOUT = 2 A 0.5 %/V VLOADREG3 Load regulation-DC IOUT = (10-90%) x IOUT_max 0.5 %/A Gm_EA3 Error amplifier trans-conductance -2 µA < ICOMP < 2 µA 1350 µs Gm_SRC3 COMP voltage to inductor current Gm ILX = 0.5 A 10 A/V ISSx Soft-start pin charging current SS1, SS2 6 µA ILIMIT1 Buck 1 peak inductor current limit 7 A ILIMIT2 Buck 2 peak inductor current limit 7 A ILIMITLSx Low side sinking current limit -2.6 A Rdsonx_HS On resistance of high side FET V7V = 6.3 V 31 m Ω Rdsonx_LS On resistance of low side FET VIN = 12 V 23 m Ω Tminon Minimum on time 94 ns VbootUV Boot-LX UVLO 2.1 3 V Thiccupwait Hiccup wait time 512 cycles Thiccup_re Hiccup time before re-start 16384 cycles I2C READ BACK FAULT STATUS Feedback lower voltage rising 94 (with respect to 0.6 V ) Feedback lower voltage falling 92.5 (with respect to 0.6 V) VPGOOD PGOOD trip levels % Feedback upper voltage rising 107.5 (with respect to 0.6 V) Feedback upper voltage falling 105.5 (with respect to 0.6 V) Twarn Temperature warning threshold 125 °C THERMAL SHUTDOWN TTRIP Thermal protection trip point Rising temperature 160 °C THYST Thermal protection hysteresis 20 °C I2C INTERFACE 0x60H if ADDR = 0; Address 0x61H if ADDR = high; 0x62H if ADDR = open VIH SDA, SCL Input high voltage 1.3 V VIL SDA, SCL Input low voltage 0.4 V II Input current SDA, SCL, VI = 0.4 V to 4.5 V -10 10 µA VOL SDA SDA output low voltage SDA open drain, IOL = 4 mA 0.4 V f(SCL) Maximum SCL clock frequency 400 kHz Bus free time between a STOP and tBUF 1.3 µs START condition Hold time (Repeated) START tHD_STA 0.6 µs condition tSU_STO Setup time for STOP condition 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs Setup time for a repeated START tSU_STA 0.6 µs condition Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TPS65279V |
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