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LMH6601 Datasheet(PDF) 5 Page - Texas Instruments |
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LMH6601 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 40 page  LMH6601, LMH6601-Q1 www.ti.com SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 Electrical Characteristics, 5 V (continued) Single-Supply with VS= 5 V, AV = +2, RF = 604 Ω, SD tied to V +, V OUT = VS/2, RL = 150 Ω to V − unless otherwise specified.(1) PARAMETER TEST CONDITIONS MIN(2) TYP(2) MAX(2) UNIT DISTORTION and NOISE PERFORMANCE HD2 2 VPP, 10 MHz −56 Harmonic Distortion (2nd) dBc HD2_1 4 VPP, 10 MHz, RL = 1 kΩ to VS/2 −61 HD3 2 VPP, 10 MHz −73 Harmonic Distortion (3rd) dBc HD3_1 4 VPP, 10 MHz, RL = 1 kΩ to VS/2 −64 THD Total Harmonic Distortion 4 VPP, 10 MHz, RL = 1 kΩ to VS/2 −58 VN1 >10 MHz 7 Input Voltage Noise nV/ √Hz VN2 1 MHz 10 IN Input Current Noise >1 MHz 50 fA/ √Hz STATIC, DC PERFORMANCE ±1 ±2.4 VIO Input Offset Voltage mV At temperature extremes ±5 DVIO Input Offset Voltage Average Drift See (3) −5 μV/°C IB Input Bias Current See (4) 5 50 pA IOS Input Offset Current See (4) 2 25 pA RIN Input Resistance 0 V ≤ VIN ≤ 3.5 V 10 T Ω CIN Input Capacitance 1.3 pF 55 59 Positive Power Supply Rejection +PSRR DC dB At temperature Ratio 51 extremes 53 61 Negative Power Supply Rejection −PSRR DC dB At temperature Ratio 50 extremes 56 68 CMRR Common-Mode Rejection Ratio DC dB At temperature 53 extremes CMRR > 50 dB (At temperature CMVR Input Voltage Range V− – 0.20 – V+ – 1.5 V extremes) 9.6 11.5 Normal Operation mA At temperature VOUT = VS/2 13.5 ICC Supply Current extremes Shutdown 100 nA SD tied to ≤ 0.5 V (5) –210 –190 VOH1 RL = 150 Ω to V – At temperature –480 extremes Output High Voltage VOH2 RL = 75 Ω to VS/2 –190 mV (Relative to V+) –60 –12 VOH3 RL = 10 kΩ to V – At temperature –110 extremes (3) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change. (4) This parameter is ensured by design and/or characterization and is not tested in production. (5) SD logic is CMOS compatible. To ensure proper logic level and to minimize power supply current, SD should typically be less than 10% of total supply voltage away from either supply rail. Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LMH6601 LMH6601-Q1 |
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