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LMP92064SD Datasheet(PDF) 6 Page - Texas Instruments |
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LMP92064SD Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 29 page  R/ A14 A13 A12 A11 A10 A9 A8 D2 D1 D0 t S t DS t HI t LO DON’T CARE DON’T CARE SCLK SDI CSB t C t DH 1/f CLK DON’T CARE DON’T CARE W DATA BIT N tDV SCLK SDO CSB DATA BIT N - 1 BIT N t S t DS t LOW SCLK SDI CSB t C t DH 1/f CLK BIT N - 1 t HIGH LMP92064 SNOSCX0A – JUNE 2013 – REVISED DECEMBER 2014 www.ti.com 6.6 Timing Requirements Typical specifications are at 25ºC. All specifications are at 4.5 V ≤ VDD ≤ 5.5 V, VDIG = VDD and a 20 pF capacitive load on SDO, unless otherwise specified. MIN MAX UNIT tDS SDI to SCLK rising edge setup time 10 ns tDH SCLK rising edge to SDI hold time 10 ns fCLK Frequency of SCLK 100 Hz 20 MHz tHIGH High width of SPI clock 25 ns tLOW Low width of SPI clock 25 ns tS CSB falling edge to SCLK rising edge setup time 10 ns tC SCLK rising edge to CSB rising edge hold time 30 ns tDV SCLK falling edge to valid SDO readback data 20 ns tRST Reset pin pulse width 3.5 ns tCONV Conversion rate of all channels 125 kSps Figure 1. Serial Control Port Timing – Write Figure 2. Serial Control Port Timing – Read Figure 3. Serial Control Port Write – MSB First, 16-Bit Instruction, Timing Measurements 6 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LMP92064 |
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