TPA3110D2

SLOS528E – JULY 2009 – REVISED NOVEMBER 2015

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Pin Functions (continued)

PIN

TYPE

DESCRIPTION

NO.

NAME

Power supply for right channel H-bridge. Right channel and left channel power supply inputs are

15

PVCCR

P

connect internally.

Power supply for right channel H-bridge. Right channel and left channel power supply inputs are

16

PVCCR

P

connect internally.

17

BSPR

I

Bootstrap I/O for right channel, positive high-side FET.

18

OUTPR

O

Class-D H-bridge positive output for right channel.

19

PGND

—

Power ground for the H-bridges.

20

OUTNR

O

Class-D H-bridge negative output for right channel.

21

BSNR

I

Bootstrap I/O for right channel, negative high-side FET.

22

BSNL

I

Bootstrap I/O for left channel, negative high-side FET.

23

OUTNL

O

Class-D H-bridge negative output for left channel.

24

PGND

—

Power ground for the H-bridges.

25

OUTPL

O

Class-D H-bridge positive output for left channel.

26

BSPL

I

Bootstrap I/O for left channel, positive high-side FET.

Power supply for left channel H-bridge. Right channel and left channel power supply inputs are

27

PVCCL

P

connect internally.

Power supply for left channel H-bridge. Right channel and left channel power supply inputs are

28

PVCCL

P

connect internally.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

Supply voltage

AVCC, PVCC

–0.3 V

30 V

V

–0.3 V

V

0.3 V

< 10

V/ms

Interface pin voltage

PLIMIT

GVDD +

–0.3

V

0.3

RINN, RINP, LINN, LINP

–0.3

6.3

V

See Thermal

Continuous total power dissipation

Information

BTL: PVCC > 15 V

4.8

Minimum Load Resistance

BTL: PVCC

≤ 15 V

3.2

PBTL

3.2

Operating free-air temperature

–40

85

°C

–40

150

°C

Storage temperature

–65

150

°C

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100-k

Ω resister in series

with the pins.

(3)

The TPA3110D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected

to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection

shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad.

4

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