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TPA3112D1QPWPRQ1 Datasheet(PDF) 3 Page - Texas Instruments

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No. de Pieza. TPA3112D1QPWPRQ1
Descripción  Filter-Free Mono Class-D Audio Power Amplifier
Descarga  32 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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TPA3112D1QPWPRQ1 Datasheet(HTML) 3 Page - Texas Instruments

 
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SD
FAULT
GND
GND
GAIN0
GAIN1
AVCC
AGND
GVDD
PLIMIT
PVCC
PVCC
BSN
OUTN
PGND
OUTN
BSN
BSP
OUTP
PGND
INN
INP
NC
11
12
13
14
18
17
16
15
OUTP
BSP
PVCC
PVCC
AVCC
TPA3112D1-Q1
www.ti.com
SLOS793B – SEPTEMBER 2012 – REVISED SEPTEMBER 2015
5 Pin Configuration and Functions
PWP Package
28-Pin HTSSOP With PowerPAD™ IC
Top View
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels
1
SD
I
with compliance to AVCC.
Open drain output used to display short circuit or DC detect fault status. Voltage compliant to AVCC.
2
FAULT
O
Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise both
the short circuit faults and DC detect faults must be reset by cycling PVCC.
3
GND
Connect to local ground.
4
GND
Connect to local ground.
5
GAIN0
I
Gain select least significant bit. TTL logic levels with compliance to AVCC.
6
GAIN1
I
Gain select most significant bit. TTL logic levels with compliance to AVCC.
7
AVCC
P
Analog supply
8
AGND
Analog supply ground. Connect to the thermal pad.
High-side FET gate drive supply. Nominal voltage is 7 V. May also be used as supply for PLIMIT
9
GVDD
O
divider. Add a 1-
μF cap to ground at this pin.
Power limit level adjust. Connect directly to GVDD pin for no power limiting. Add a 1-
μF cap to
10
PLIMIT
I
ground at this pin.
11
INN
I
Negative audio input. Biased at 3 V.
12
INP
I
Positive audio input. Biased at 3 V.
13
NC
Not connected
14
AVCC
P
Connect AVCC supply to this pin.
15
PVCC
P
Power supply for H-bridge. PVCC pins are also connected internally.
16
PVCC
P
Power supply for H-bridge. PVCC pins are also connected internally.
17
BSP
I
Bootstrap I/O for positive high-side FET.
18
OUTP
O
Class-D H-bridge positive output.
19
PGND
Power ground for the H-bridges.
20
OUTP
O
Class-D H-bridge positive output.
21
BSP
I
Bootstrap I/O for positive high-side FET.
22
BSN
I
Bootstrap I/O for negative high-side FET.
23
OUTN
O
Class-D H-bridge negative output.
24
PGND
Power ground for the H-bridges.
25
OUTN
O
Class-D H-bridge negative output.
26
BSN
I
Bootstrap I/O for negative high-side FET.
27
PVCC
P
Power supply for H-bridge. PVCC pins are also connected internally.
28
PVCC
P
Power supply for H-bridge. PVCC pins are also connected internally.
Copyright © 2012–2015, Texas Instruments Incorporated
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