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AD9655BCPZ-125 Datasheet(PDF) 9 Page - Analog Devices |
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AD9655BCPZ-125 Datasheet(HTML) 9 Page - Analog Devices |
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9 / 37 page  Data Sheet AD9655 Timing Diagrams D0A– D0A+ D1A– D1A+ FCO– BYTEWISE MODE FCO+ D0A– D0A+ D1A– D1A+ FCO– DCO– DCO+ DCO+ CLK+ VINx± CLK– DCO– FCO+ BITWISE MODE SDR DDR MSB N – 17 D14 N – 17 D13 N – 17 D12 N – 17 D11 N – 17 D10 N – 17 D09 N – 17 D08 N – 17 MSB N – 16 D14 N – 16 D13 N – 16 D12 N – 16 D11 N – 16 D10 N – 16 D09 N – 16 D08 N – 16 D07 N – 17 D06 N – 17 D05 N – 17 D04 N – 17 D03 N – 17 D2 N – 17 D01 N – 17 LSB N – 17 D07 N – 16 D06 N – 16 D05 N – 16 D04 N – 16 D03 N – 16 D02 N – 16 D01 N – 16 LSB N – 16 MSB N – 17 D13 N – 17 D11 N – 17 D09 N – 17 D07 N – 17 D05 N – 17 D03 N – 17 D01 N – 17 MSB N – 16 D13 N – 16 D11 N – 16 D09 N – 16 D07 N – 16 D05 N – 16 D03 N – 16 D01 N – 16 D14 N – 17 D12 N – 17 D10 N – 17 D08 N – 17 D06 N – 17 D04 N – 17 D02 N – 17 LSB N – 17 D14 N – 16 D12 N – 16 D10 N – 16 D08 N – 16 D06 N – 16 D04 N – 16 D02 N – 16 LSB N – 16 tA tDATA tEH tFCO tFRAME tPD tCPD tEL N – 1 N N + 1 Figure 2. 16-Bit DDR/Single Data Rate (SDR), Two-Lane, 1× Frame Mode (Default) D0x– D0x+ FCO– DCO+ CLK+ VINx± CLK– DCO– FCO+ D14 N – 17 MSB N – 17 D13 N – 17 D12 N – 17 D11 N – 17 D10 N – 17 D9 N – 17 D8 N – 17 D7 N – 17 D6 N – 17 D5 N – 17 D4 N – 17 D3 N – 17 D2 N – 17 D1 N – 17 LSB N – 17 MSB N – 16 D14 N – 16 D13 N – 16 tA tDATA tEH tFCO tFRAME tPD tCPD tEL N – 1 N Figure 3. Wordwise DDR, One-Lane, 1× Frame, 16-Bit Output Mode Rev. 0 | Page 9 of 37 |
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