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LMX2492RTWR Datasheet(PDF) 6 Page - Texas Instruments |
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LMX2492RTWR Datasheet(HTML) 6 Page - Texas Instruments |
6 / 42 page tCES tCS R/W A14 A13 tCH tCWH tCWL A0 D7 D1 D0 MSB LSB DATA CLK LE tCE tEWH A12 A11 LMX2492, LMX2492-Q1 SNAS624B – MARCH 2014 – REVISED MAY 2015 www.ti.com Electrical Characteristics (continued) (3.15 V ≤ Vcc ≤ 3.45 V. Vcc ≤Vcp ≤5.25 V. Typical values are at Vcc = Vcp = 3.3 V, 25 °C. -40°C ≤ TA ≤ 85 °C for the LMX2492 and -40°C ≤ TA ≤ 125 °C for the LMX2492-Q1 ; except as specified.) PARAMETER CONDITIONS MIN TYP MAX UNIT LOGIC OUTPUT TERMINALS (MUXout,TRIG1,TRIG2,MOD) 0.8 x VOH Output High Voltage Vcc V Vcc VOL Output Low Voltage 0 0.2 x Vcc V LOGIC INPUT TERMINALS (CE,CLK,DATA,LE,MUXout,TRIG1,TRIG2,MOD) VIH Input High Voltage 1.4 Vcc V VIL Input Low Voltage 0 0.6 V IIH Input Leakage -5 1 5 uA TCELOW Chip enable Low Time 5 us TCEHIGH Chip enable High Time 5 us 7.7 Timing Requirements, Programming Interface (CLK, DATA, LE) MIN NOM MAX UNIT TCE Clock To LE Low Time 10 ns TCS Data to Clock Setup Time 4 ns TCH Data to Clock Hold Time 4 ns TCWH Clock Pulse Width High 10 ns TCWL Clock Pulse Width Low 10 ns TCES Enable to Clock Setup Time 10 ns TEWH Enable Pulse Width High 10 ns Figure 1. Serial Data Input Timing There are several other considerations for programming: • The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is sent from the shift register to an actual counter. • If no LE signal is given after the last data bit and the clock is kept toggling, then these bits will be read into the next lower register. This eliminates the need to send the address each time. • A slew rate of at least 30 V/us is recommended for the CLK, DATA, and LE signals • Timing specifications also apply to readback. Readback can be done through the MUXout, TRIG1, TRIG2, or MOD terminals. 6 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 |
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