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LMX2531LQE1226E Datasheet(PDF) 4 Page - Texas Instruments |
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LMX2531LQE1226E Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 48 page  LMX2531 SNAS252S – OCTOBER 2005 – REVISED DECEMBER 2014 www.ti.com Pin Functions PIN TYPE DESCRIPTION NAME NO. Chip Enable Input. High impedance CMOS input. This pin must not exceed 2.75 V. When CE is brought high the LMX2531 is powered up corresponding to the internal power control CE 11 Input bits. Although the part can be programmed when powered down, it is still necessary to reprogram the R0 register to get the part to re-lock. MICROWIRE clock input. High impedance CMOS input. This pin must not exceed 2.75 V. CLK 9 Input Data is clocked into the shift register on the rising edge. Charge pump output for PLL. For connection to Vtune through an external passive loop CPout 24 Output filter. MICROWIRE serial data input. High impedance CMOS input. This pin must not exceed DATA 8 Input 2.75 V. Data is clocked in MSB first. The last bits clocked in form the control or register select bits. FLout 25 Output An open drain NMOS output which is used for FastLock or a general purpose output. Fout 21 Output Buffered RF Output for the VCO. Ftest/LD 30 Output Multiplexed CMOS output. Typically used to monitor PLL lock condition. GND 3 — Ground GND 19 — Ground for the VCO circuitry. GND 20 — Ground for the VCO Output Buffer circuitry. GND 34 — Ground MICROWIRE Latch Enable input. High impedance CMOS input. This pin must not exceed LE 10 Input 2.75 V. Data stored in the shift register is loaded into the selected latch register when LE goes HIGH. 2, 4, 5, 7, 12, NC — No Connect. 13, 29, 35 NC 14, 15 — No Connect. Do NOT ground. This also includes the pad above these pins. OSCin 31 Input Oscillator input. Oscillator complimentary input. When a single ended source is used, then a bypass OSCin* 32 Input capacitor should be placed as close as possible to this pin and be connected to ground. Test 33 Output This pin is for test purposes and should be grounded for normal operation. Power Supply for the VCO Buffer circuitry. Input may range from 2.8 — 3.2 V. Bypass VccBUF 22 — capacitors should be placed as close as possible to this pin and ground. Power Supply for digital LDO circuitry. Input may range from 2.8 — 3.2 V. Bypass VccDIG 1 — capacitors should be placed as close as possible to this pin and ground. Power Supply for the PLL. Input may range from 2.8 — 3.2 V. Bypass capacitors should be VccPLL 27 — placed as close as possible to this pin and ground. Power Supply for VCO regulator circuitry. Input may range from 2.8 — 3.2 V. Bypass VccVCO 16 — capacitors should be placed as close as possible to this pin and ground. Internal reference voltage for VCO LDO. Not intended to drive an external load. Connect to VrefVCO 18 — ground with a capacitor. Internally regulated voltage for the VCO buffer circuitry. Connect to ground with a VregBUF 6 — capacitor. VregDIG 36 — Internally regulated voltage for LDO digital circuitry. Internally regulated voltage for PLL charge pump. Not intended to drive an external load. VregPLL1 26 — Connect to ground with a capacitor. Internally regulated voltage for RF digital circuitry. Not intended to drive an external load. VregPLL2 28 — Connect to ground with a capacitor. Internally regulated voltage for VCO circuitry. Not intended to drive an external load. VregVCO 17 — Connect to ground with a capacitor and some series resistance. Tuning voltage input for the VCO. For connection to the CPout pin through an external Vtune 23 Input passive loop filter. 4 Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: LMX2531 |
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