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DLP4500 Datasheet(PDF) 11 Page - Texas Instruments

No. de pieza DLP4500
Descripción Electrónicos  WXGA
Download  57 Pages
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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DLP4500 Datasheet(HTML) 11 Page - Texas Instruments

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DLP4500
www.ti.com
DLPS028B – APRIL 2013 – REVISED JANUARY 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
SUPPLY VOLTAGES (2)
VCC
Supply voltage for LVCMOS core logic
–0.5
4
V
VREF
Supply voltage for LVCMOS DDR interface
–0.5
4
V
VOFFSET
Supply voltage for high voltage CMOS and micromirror electrode
–0.5
8.75
V
VBIAS (3)
Supply voltage for micromirror electrode
–0.5
17
V
VRESET
Supply voltage for micromirror electrode
–11
0.5
V
|VBIAS - VOFFSET| (3)
Supply voltage delta (absolute value)
8.75
V
INPUT VOLTAGES (2)
Input voltage to all other input pins
–0.5
VREF + 0.5
V
INPUT CURRENTS
Current required from a high-level output
VOH = 1.4 V
–9
mA
Current required from a low-level output
VOL = 0.4 V
18
mA
CLOCKS
fCLK
DCLK clock frequency
80
120
MHz
ENVIRONMENTAL
Case temperature - operational (4)
-20
90
°C
TCASE
Case temperature - non-operational (4)
-40
90
°C
TDP
Dew Point (operation and non-operational)
81
°C
Operating Relative Humidity (non-condensing)
0
95
%RH
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device is not implied at these or any conditions beyond those indicated under Recommended
Operating Conditions. Exposure above Recommended Operating Conditions for extended periods may affect device reliability.
(2)
All voltage values are referenced to common ground VSS. Supply voltages VCC, VREF, VOFFSET, VBIAS, and VRESET are all
required for proper DMD operation. VSS must also be connected.
(3)
To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.
(4)
DMD Temperature is the worst-case of any test point shown in Figure 9 or Figure 10, or the active array as calculated by the
Micromirror Array Temperature Calculation, or any point along the Window Edge as defined in Figure 9 or Figure 10. The locations of
thermal test point TP2 is intended to measure the highest window edge temperature. If a particular application causes another point on
the window edge to be at a higher temperature, a test point should be added to that location.
6.2 Storage Conditions
applicable before the DMD is installed in the final product
MIN
MAX
UNIT
Storage temperature (1)
–40
85
°C
Storage humidity, non-condensing (1)
0
95
%RH
Tstg
Long-term storage dew point (1) (2)
24
°C
Short-term storage dew point (1) (3)
28
°C
(1)
As a best practice, TI recommends storing the DMD in a temperature and humidity controlled environment.
(2)
Long-term is defined as the average over the usable life.
(3)
Short-term is defined as <60 cumulative days over the usable life of the device.
6.3 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) (2) (3)
±2000
V
(1)
ESD Ratings are applicable before the DMD is installed in final product.
(2)
All CMOS devices require proper Electrostatic Discharge (ESD) handling procedures.
(3)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
Copyright © 2013–2016, Texas Instruments Incorporated
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