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DLP9500BFLN Datasheet(PDF) 5 Page - Texas Instruments |
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DLP9500BFLN Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 54 page  DLP9500 www.ti.com DLPS025C – AUGUST 2012 – REVISED SEPTEMBER 2015 Pin Functions PIN (1) TYPE DATA INTERNAL TERM TRACE SIGNAL CLOCK DESCRIPTION (I/O/P) RATE (2) (3) (MILS) NAME NO. DATA BUS A Differentially D_AN(0) F2 Input LVCMOS DDR DCLK_A 512.01 terminated – 100 Ω Differentially D_AN(1) H8 Input LVCMOS DDR DCLK_A 158.79 terminated – 100 Ω Differentially D_AN(2) E5 Input LVCMOS DDR DCLK_A 471.24 terminated – 100 Ω Differentially D_AN(3) G9 Input LVCMOS DDR DCLK_A 159.33 terminated – 100 Ω Differentially D_AN(4) D2 Input LVCMOS DDR DCLK_A 585.41 terminated – 100 Ω Differentially D_AN(5) G3 Input LVCMOS DDR DCLK_A 551.17 terminated – 100 Ω Differentially D_AN(6) E11 Input LVCMOS DDR DCLK_A 229.41 terminated – 100 Ω Differentially D_AN(7) F8 Input LVCMOS DDR DCLK_A 300.54 terminated – 100 Ω Differentially D_AN(8) C9 Input LVCMOS DDR DCLK_A 346.35 terminated – 100 Ω Differentially D_AN(9) H2 Input LVCMOS DDR DCLK_A 782.27 terminated – 100 Ω Differentially D_AN(10) B10 Input LVCMOS DDR DCLK_A 451.52 terminated – 100 Ω Differentially D_AN(11) G15 Input LVCMOS DDR DCLK_A 74.39 terminated – 100 Ω Differentially D_AN(12) D14 Input LVCMOS DDR DCLK_A 194.26 terminated – 100 Ω Input data bus A Differentially D_AN(13) F14 Input LVCMOS DDR DCLK_A 148.29 terminated – 100 Ω (2x LVDS) Differentially D_AN(14) C17 Input LVCMOS DDR DCLK_A 244.9 terminated – 100 Ω Differentially D_AN(15) H16 Input LVCMOS DDR DCLK_A 73.39 terminated – 100 Ω Differentially D_AP(0) F4 Input LVCMOS DDR DCLK_A 509.63 terminated – 100 Ω Differentially D_AP(1) H10 Input LVCMOS DDR DCLK_A 152.59 terminated – 100 Ω Differentially D_AP(2) E3 Input LVCMOS DDR DCLK_A 464.09 terminated – 100 Ω Differentially D_AP(3) G11 Input LVCMOS DDR DCLK_A 152.39 terminated – 100 Ω Differentially D_AP(4) D4 Input LVCMOS DDR DCLK_A 591.39 terminated – 100 Ω Differentially D_AP(5) G5 Input LVCMOS DDR DCLK_A 532.16 terminated – 100 Ω Differentially D_AP(6) E9 Input LVCMOS DDR DCLK_A 230.78 terminated – 100 Ω Differentially D_AP(7) F10 Input LVCMOS DDR DCLK_A 300.61 terminated – 100 Ω Differentially D_AP(8) C11 Input LVCMOS DDR DCLK_A 338.16 terminated – 100 Ω Differentially D_AP(9) H4 Input LVCMOS DDR DCLK_A 773.17 terminated – 100 Ω Differentially D_AP(10) B8 Input LVCMOS DDR DCLK_A 449.57 terminated – 100 Ω (1) The following power supplies are required to operate the DMD: VCC, VCC1, VCC2. VSS must also be connected. (2) DDR = Double Data Rate. SDR = Single Data Rate. Refer to the LVDS Timing Requirements for specifications and relationships. (3) Refer to Electrical Characteristics for differential termination specification Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: DLP9500 |
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