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DLPC150 Datasheet(PDF) 9 Page - Texas Instruments

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No. de pieza DLPC150
Descripción Electrónicos  Digital Controller for Advanced Light Control
Download  55 Pages
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

DLPC150 Datasheet(HTML) 9 Page - Texas Instruments

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DLPC150
www.ti.com
DLPS048B – MARCH 2015 – REVISED OCTOBER 2015
Pin Functions (continued)
PIN
I/O(1)
DESCRIPTION
NAME
NO.
General purpose I/O 05 (hysteresis buffer). Option:
GPIO_05
E15
B1
1.
Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not
used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).
CLOCK AND PLL SUPPORT
Reference clock crystal input. If an external oscillator is used in place of a crystal, then this pin
PLL_REFCLK_I
H1
I11
serves as the oscillator input.
Reference clock crystal return. If an external oscillator is used in place of a crystal, then leave this
PLL_REFCLK_O
J1
O5
pin unconnected with no capacitive load.
BOARD LEVEL TEST AND DEBUG
Reserved Manufacturing test enable pin. For proper device operation, connect this signal directly to
HWTEST_EN
C10
I6
ground.
Reserved
P12
I6
Reserved pin. For proper device operation, leave this pin unconnected.
Reserved
P13
I6
Reserved pin. For proper device operation, leave this pin unconnected.
Reserved
N13(6)
O1
Reserved pin. For proper device operation, leave this pin unconnected.
Reserved
N12(6)
O1
Reserved pin. For proper device operation, leave this pin unconnected.
Reserved
R10
B8
Reserved pin. For proper device operation, pull high to Vcc18 with external pullup resistor.
Reserved
R11
B8
Reserved pin. For proper device operation, pull high to Vcc18 with external pullup resistor.
Reserved
M13
I6
Reserved pin. For proper device operation, leave this pin unconnected.
Reserved
N11
I6
Reserved pin. For proper device operation, leave this pin unconnected.
Reserved pin.
Reserved
P11
I6
For proper device operation, this pin must be tied to ground, through an external 8-k
Ω, or less,
resistor. Failure to tie this pin low will cause startup and initialization problems.
Reserved
E1
Reserved pin. For proper device operation, leave this pin unconnected.
Reserved
E2
Reserved pin. For proper device operation, leave this pin unconnected.
Reserved
F1
Reserved pin. For proper device operation, leave this pin unconnected.
Reserved
F2
Reserved pin. For proper device operation, leave this pin unconnected.
Reserved
F3
Reserved pin. For proper device operation, leave this pin unconnected.
Reserved
G1
Reserved pin. For proper device operation, leave this pin unconnected.
Reserved
G2
Reserved pin. For proper device operation, leave this pin unconnected.
Reserved
D1
Reserved pin. For proper device operation, leave this pin unconnected.
Reserved
D2
Reserved pin. For proper device operation, leave this pin unconnected.
Reserved
C1
Reserved pin. For proper device operation, leave this pin unconnected.
Reserved
C2
Reserved pin. For proper device operation, leave this pin unconnected.
Reserved Test pin 0. For proper device operation, leave this pin unconnected (includes weak
internal pulldown).Tri-stated while RESETZ is asserted low. Sampled as an input test mode
TSTPT_0
R12
B1
selection control approximately 1.5 µs after de-assertion of RESETZ, and then driven as an output.
Note: An external pullup should not be applied to this pin to avoid putting the DLPC150 in a test
mode.
Reserved Test pin 1. For proper device operation, leave this pin unconnected (includes weak
internal pulldown). Tri-stated while RESETZ is asserted low. Sampled as an input test mode
TSTPT_1
R13
B1
selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.
Note: An external pullup should not be applied to this pin to avoid putting the DLPC150 in a test
mode.
Reserved Test pin 2. For proper device operation, leave this pin unconnected (includes weak
internal pulldown). Tri-stated while RESETZ is asserted low. Sampled as an input test mode
TSTPT_2
R14
B1
selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.
Note: An external pullup should not be applied to this pin to avoid putting the DLPC150 in a test
mode.
(6)
If operation does not call for an external pullup and there is no external logic that might overcome the weak internal pulldown resistor,
then this I/O can be left open or unconnected for normal operation. If operation does not call for an external pullup, but there is external
logic that might overcome the weak internal pulldown resistor, then an external pulldown resistor is recommended to ensure a logic low.
Copyright © 2015, Texas Instruments Incorporated
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