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DLPC350ZFF Datasheet(PDF) 8 Page - Texas Instruments |
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DLPC350ZFF Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 62 page  DLPC350 DLPS029C – APRIL 2013 – REVISED MARCH 2014 www.ti.com Terminal Function Descriptions (continued) TERMINAL(1) I/O I/O CLK TYPE INTERNAL TERMINATION DESCRIPTION POWER SYSTEM NAME NUMBER (2) LEDR_EN L3 LED red PWM output LEDG_EN L4 VDD33 O2 Async LED green PWM output LEDB_EN K1 LED blue PWM output TRIGGER CONTROL In trigger mode 1, this signal is used to advance the pattern display. In trigger mode 2, the rising edge TRIG_IN_1 G19 VDD33 B2 Async displays the pattern and the falling edge displays the next indexed pattern. In trigger mode 1, this signal is used to start (rising edge) and stop (falling edge) the pattern display. It TRIG_IN_2 F22 VDD33 B2 Async works along with the software start and stop command. In trigger mode 2, this signal is used to advance the pattern by two indexes. TRIG_OUT_1 C17 VDD33 B2 Async Active high trigger output signal during pattern exposure TRIG_OUT_2 K21 VDD33 B2 Async Active high trigger output to indicate first pattern display PERIPHERAL INTERFACE USB D– I/O for USB command interface. TI strongly recommends a 5.0-W external series resistance (of 22 Ω) to limit the potential impact of a continuous short USB_DAT_N E3 circuit between USB_DAT_N and either VBUS, GND, the other data line, or the cable. For additional protection, an optional 200-mA Shottky diode from USB_DAT_N to VDD33 can also be added. VDD33 B9 Async USB D+ I/O for USB command interface. TI strongly recommends a 5.0-W external series resistance (of 22 Ω) to limit the potential impact of a continuous short USB_DAT_P E2 circuit between USB_DAT_P and either VBUS, GND, the other data line, or the cable. For additional protection, an optional 200-mA Shottky diode from USB_DAT_P to VDD33 can also be added. USB_EN C18 VDD33 B2 Async USB enable UART_TXD L19 VDD33 O2 Async Transmit data output. Reserved for debug messages UART_RXD L21 VDD33 I4 Async Receive data input. Reserved for debug messages Ready to send hardware flow control output. Reserved UART_RTS M19 VDD33 O2 Async for debug messages Clear to send hardware flow control input. Reserved for UART_CTS L20 VDD33 I4 Async debug messages GPIOS (7) ALTERNATIVE MODE GPIO_36 G1 VDD33 B2 Async None GPIO_35 H4 VDD33 B2 Async None GPIO_34 H3 VDD33 B2 Async None GPIO_33 H2 VDD33 B2 Async None GPIO_29 F20 VDD33 B2 Async None GPIO_28 E22 VDD33 B2 Async None GPIO_27 E21 VDD33 B2 Async None GPIO_25 D22 VDD33 B2 Async None GPIO_24 E20 VDD33 B2 Async None GPIO_21 N20 VDD33 B2 Async None GPIO_20 N19 VDD33 B2 Async None GPIO_15 B19 VDD33 B2 Async None GPIO_14 B18 VDD33 B2 Async None GPIO_13 L2 VDD33 B2 Async None GPIO_12 M4 VDD33 B2 Async OCLKD (Output) (7) GPIO signals must be configured via software for input, output, bidirectional, or open-drain. Some GPIOs have one or more "alternative use" modes which are also software configurable. The reset default for all optional GPIOs is as an input signal. However, any alternate function connected to these GPIO pins with the exception of General Purpose Clocks and PWM Generation, will be reset. An external pullup to the 3.3-V supply is required for each signal configured as open-drain. External pullup or pulldown resistors may be required to ensure stable operation before software is able to configure these ports. 8 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: DLPC350 |
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