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DLPC3435CZEZ Datasheet(PDF) 11 Page - Texas Instruments |
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DLPC3435CZEZ Datasheet(HTML) 11 Page - Texas Instruments |
11 / 59 page 11 DLPC3430, DLPC3435 www.ti.com DLPS038B – JULY 2014 – REVISED FEBRUARY 2016 Product Folder Links: DLPC3430 DLPC3435 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Pin Functions – Clock and PLL Support PIN I/O DESCRIPTION NAME NUMBER PLL_REFCLK_I H1 I11 Reference clock crystal input. If an external oscillator is used in place of a crystal, then this pin should be used as the oscillator input. PLL_REFCLK_O J1 O5 Reference clock crystal return. If an external oscillator is used in place of a crystal, then this pin should be left unconnected (that is floating with no added capacitive load). (1) The only power sequencing restrictions are: (a) The VDDLP12 supply must be powered-on at exactly the same time or after the VDD11 supply. (b) The VDD11 supply should ramp up with a 1-ms minimum rise time. (c) The reverse is needed at power down. Pin Functions – Power and Ground(1) PIN I/O DESCRIPTION NAME NUMBER VDD C5, D5, D7, D12, J4, J12, K3, L4, L12, M6, M9, D9, D13, F13, H13, L13, M10, D3, E3 PWR Core power 1.1 V (main 1.1 V) VDDLP12 C3 PWR Core power 1.1 V VSS Common to all package types C4, D6, D8, D10, E4, E13, F4, G4, G12, H4, H12, J3, J13, K4, K12, L3, M4, M5, M8, M12, G13, C6, C8 Only available on DLPC343x F6, F7, F8, F9, F10, G6, G7, G8, G9, G10, H6, H7, H8, H9, H10, J6, J7, J8, J9, J10, K6, K7, K8, K9, K10 GND Core ground (eDRAM, I/O ground, thermal ground) VCC18 C7, C9, D4, E12, F12, K13, M11 PWR All 1.8-V I/O power: (1.8-V power supply for all I/O other than the host or parallel interface and the SPI flash interface. This includes RESETZ, PARKZ LED_SEL, CMP, GPIO, IIC1, TSTPT, and JTAG pins) VCC_INTF M3, M7, N3, N7 PWR Host or parallel interface I/O power: 1.8 to 3.3 V (Includes IIC0, PDATA, video syncs, and HOST_IRQ pins) VCC_FLSH D11 PWR Flash interface I/O power:1.8 to 3.3 V (Dedicated SPI0 power pin) VDD_PLLM H2 PWR MCG PLL 1.1-V power VSS_PLLM G3 RTN MCG PLL return VDD_PLLD J2 PWR DCG PLL 1.1-V power VSS_PLLD H3 RTN DCG PLL return Table 1. I/O Type Subscript Definition I/O SUPPLY REFERENCE ESD STRUCTURE SUBSCRIPT DESCRIPTION 1 1.8 LVCMOS I/O buffer with 8-mA drive Vcc18 ESD diode to GND and supply rail 2 1.8 LVCMOS I/O buffer with 4-mA drive Vcc18 ESD diode to GND and supply rail 3 1.8 LVCMOS I/O buffer with 24-mA drive Vcc18 ESD diode to GND and supply rail 4 1.8 sub-LVDS output with 4-mA drive Vcc18 ESD diode to GND and supply rail 5 1.8, 2.5, 3.3 LVCMOS with 4-mA drive Vcc_INTF ESD diode to GND and supply rail 6 1.8 LVCMOS input Vcc18 ESD diode to GND and supply rail 7 1.8-, 2.5-, 3.3-V I2C with 3-mA drive Vcc_INTF ESD diode to GND and supply rail 8 1.8-V I2C with 3-mA drive Vcc18 ESD diode to GND and supply rail 9 1.8-, 2.5-, 3.3-V LVCMOS with 8-mA drive Vcc_INTF ESD diode to GND and supply rail 11 1.8, 2.5, 3.3 LVCMOS input Vcc_INTF ESD diode to GND and supply rail 12 1.8-, 2.5-, 3.3-V LVCMOS input Vcc_FLSH ESD diode to GND and supply rail 13 1.8-, 2.5-, 3.3-V LVCMOS with 8-mA drive Vcc_FLSH ESD diode to GND and supply rail |
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