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TS3006ITD833T Datasheet(PDF) 7 Page - Silicon Laboratories

No. de pieza TS3006ITD833T
Descripción Electrónicos  Single Resistor Sets Output Frequency
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Fabricante Electrónico  SILABS [Silicon Laboratories]
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TS3006ITD833T Datasheet(HTML) 7 Page - Silicon Laboratories

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TS3006
TS3006 Rev. 1.0
Page 7
THEORY OF OPERATION
The TS3006 is a user-programmable oscillator where
the period of the square wave at its FOUT terminal is
generated by an external resistor connected to the
RSET pin. The output frequency is given by:
FOUT (kHz)
1.08E11
RSET
Equation 1. FOUT Frequency Calculation
With an RSET = 4.32M
Ω, the output frequency is
approximately 25kHz with a 50% duty cycle. As
design aids, Tables 1 lists TS3006’s typical FOUT for
various standard values for RSET.
Connect CPWM to VDD to disable the PWM function
and in turn, save power. Connect PWM_CNTRL to
VDD for a fixed PWMOUT output pulse width, which
is determined by the CPWM pin capacitor only.
APPLICATIONS INFORMATION
Minimizing Power Consumption
To keep the TS3006’s power consumption low,
resistive loads at the FOUT and PWMOUT terminals
increase dc power consumption and therefore should
be as large as possible. Capacitive loads at the
FOUT
and
PWMOUT
terminals
increase
the
TS3006’s transient power consumption and, as well,
should be as small as possible.
One challenge to minimizing the TS3006’s transient
power consumption is the probe capacitance of
oscilloscopes and frequency counter instruments.
Most instruments exhibit an input capacitance of
15pF or more. Unless buffered, the increase in
transient load current can be as much as 400nA.
To minimize capacitive loading, the technique shown
in Figure 1 can be used. In this circuit, the principle of
series-connected capacitors can be used to reduce
the effective capacitive load at the TS3006’s FOUT
and PWMOUT terminals.
To determine the optimal value for CEXT once the
probe capacitance is known by simply solving for
CEXT using the following expression:
For
example,
if
the
instrument’s
input
probe
capacitance is 15pF and the desired effective load
capacitance at either or both FOUT and PWMOUT
terminals is to be
≤5pF, then the value of CEXT should
be
≤7.5pF.
TS3006 Start-up Time
As the TS3006 is powered up, its FOUT terminal
(and PWMOUT terminal, if enabled) is active once
the applied VDD is higher than 1.55V. Once the
applied VDD is higher than 1.55V, the master
oscillator achieves steady-state operation within 8ms.
RSET (M
Ω) FOUT (kHz)
0.360
300
1
108
2.49
43.37
4.32
25
6.81
15.86
9.76
11.07
12
9
Table 1: FOUT vs RSET
CEXT =
1
1
CLOAD(EFF)
-
1
CPROBE
Equation 2: External Capacitor Calculation
Figure 1: Using an External Capacitor in Series with
Probes Reduces Effective Capacitive Load.


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