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CAP1128 Datasheet(PDF) 11 Page - Microchip Technology |
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CAP1128 Datasheet(HTML) 11 Page - Microchip Technology |
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11 / 75 page  2015 Microchip Technology Inc. DS00001622B-page 11 CAP1128 4.0 COMMUNICATIONS 4.1 Communications The CAP1128communicates using the 2-wire SMBus or I2C bus, the 2-wire proprietary BC-Link, or the SPI bus. If the proprietary BC-Link protocol is required for your application, please contact your Microchip representative for ordering instructions. Regardless of communication mechanism, the device functionality remains unchanged. The communica- tions mechanism as well as the SMBus (or I2C) slave address is determined by the resistor connected between the ADDR_COMM pin and ground as shown in Table 4-1. 4.1.1 SMBUS (I2C) COMMUNICATIONS When configured to communicate via the SMBus, the CAP1128 supports the following protocols: Send Byte, Receive Byte, Read Byte, Write Byte, Read Block, and Write Block. In addition, the device supports I2C formatting for block read and block write protocols. APPLICATION NOTE: For SMBus/I2C communications, the SPI_CS# pin is not used and should be grounded; any data presented to this pin will be ignored. See Section 4.2 and Section 4.3 for more information on the SMBus bus and protocols respectively. 4.1.2 SPI COMMUNICATIONS When configured to communicate via the SPI bus, the CAP1128supports both bi-directional 3-wire and normal 4-wire protocols and uses the SPI_CS# pin to enable communications. APPLICATION NOTE: See Section 4.5 and Section 4.6 for more information on the SPI bus and protocols respectively.Upon power up, the CAP1128 will not respond to any communications for up to 15ms. After this time, full functionality is available. 4.2 System Management Bus The CAP1128 communicates with a host controller, such as an SIO, through the SMBus. The SMBus is a two-wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in Figure 4-1. Stretching of the SMCLK signal is supported; however, the CAP1128 will not stretch the clock signal. TABLE 4-1: ADDR_COMM PIN DECODE Pull-Down Resistor (+/- 5%) Protocol Used SMBus Address GND SPI Communications using Normal 4-wire Protocol Used n/a 56k SPI Communications using Bi- Directional 3-wire Protocol Used n/a 68k Reserved n/a 82k SMBus / I2C 0101_100(r/w) 100k SMBus / I2C 0101_011(r/w) 120k SMBus / I2C 0101_010(r/w) 150k SMBus / I2C 0101_001(r/w) VDD SMBus / I2C 0101_000(r/w) |
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