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ADC128S022CIMT Datasheet(PDF) 7 Page - Texas Instruments |
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ADC128S022CIMT Datasheet(HTML) 7 Page - Texas Instruments |
7 / 29 page 8 9 10 11 12 13 14 15 16 Track Hold Power Up ADD2 ADD1 ADD0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DIN DOUT SCLK CS Control register 1 2 3 4 5 6 7 1 2 3 4 5 6 7 ADD2 ADD1 ADD0 8 DB11 DB10 DB9 Power Down Power Up Track Hold FOUR ZEROS FOUR ZEROS DB1 DB0 ADC128S022 www.ti.com SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015 Electrical Characteristics (continued) The following specifications apply for AGND = DGND = 0 V, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200 ksps, CL = 50 pF, unless otherwise noted. Maximum and minimum limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. (1) PARAMETER TEST CONDITIONS MIN TYP MAX(2) UNIT AC ELECTRICAL CHARACTERISTICS fSCLKMIN Minimum clock frequency VA = VD = 2.7 V to 5.25 V 0.8 MHz fSCLK Maximum clock frequency VA = VD = 2.7 V to 5.25 V 16 3.2 MHz 50 ksps fS Sample rate continuous mode VA = VD = 2.7 V to 5.25 V 1000 200 ksps tCONVERT Conversion (hold) time VA = VD = 2.7 V to 5.25 V 13 SCLK cycles 40% 30% DC SCLK duty cycle VA = VD = 2.7 V to 5.25 V 70% 60% tACQ Acquisition (track) time VA = VD = 2.7 V to 5.25 V 3 SCLK cycles Acquisition time + conversion time Throughput time 16 SCLK cycles VA = VD = 2.7 V to 5.25 V tAD Aperture delay VA = VD = 2.7 V to 5.25 V 4 ns 6.6 Timing Specifications The following specifications apply for VA = VD = 2.7 V to 5.25 V, AGND = DGND = 0 V, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200 ksps, and CL = 50 pF. Maximum and minimum limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. PARAMETER TEST CONDITIONS MIN NOM MAX(1) UNIT tCSH CS hold time after SCLK rising edge 10 0 ns tCSS CS set-up time prior to SCLK rising edge 10 4.5 ns tEN CS falling edge to DOUT enabled 5 30 ns tDACC DOUT access time after SCLK falling edge 17 27 ns tDHLD DOUT hold time after SCLK falling edge 4 ns tDS DIN set-up time prior to SCLK rising edge 10 3 ns tDH DIN hold time after SCLK rising edge 10 3 ns tCH SCLK high time 0.4 × tSCLK ns tCL SCLK low time 0.4 × tSCLK ns DOUT falling 2.4 20 ns tDIS CS rising Edge to DOUT high-impedance DOUT rising 0.9 20 ns (1) Data sheet min/max specification limits are specified by design, test, or statistical analysis. Figure 1. ADC128S022 Operational Timing Diagram Copyright © 2005–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ADC128S022 |
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