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ADC128S052CIMTX/NOPB Datasheet(PDF) 8 Page - Texas Instruments |
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ADC128S052CIMTX/NOPB Datasheet(HTML) 8 Page - Texas Instruments |
8 / 32 page tCONVERT tACQ tCH tCL tDACC tEN tDH tDS FOUR ZEROS DB10 DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC DB11 DB9 DB8 DB1 16 8 7 6 5 4 3 2 1 DB0 DIN DOUT SCLK CS tDIS tDHLD 8 9 10 11 12 13 14 15 16 Track Hold Power Up ADD2 ADD1 ADD0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DIN DOUT SCLK CS Control register 1 2 3 4 5 6 7 1 2 3 4 5 6 7 ADD2 ADD1 ADD0 8 DB11 DB10 DB9 Power Down Power Up Track Hold FOUR ZEROS FOUR ZEROS DB1 DB0 ADC128S052, ADC128S052-Q1 SNAS333E – AUGUST 2005 – REVISED DECEMBER 2015 www.ti.com 6.7 Timing Specifications The following specifications apply for VA = VD = 2.7 V to 5.25 V, AGND = DGND = 0 V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 kSPS to 500 kSPS, and CL = 50 pF. Maximum and minimum limits apply for TA = TMIN to TMAX; all other limits TA = 25°C. See Figure 1, Figure 2, and Figure 3. MIN NOM MAX(1) UNIT CS Hold Time after SCLK tCSH 10 0 ns Rising Edge CS Set-up Time prior to SCLK tCSS 10 4.5 ns Rising Edge CS Falling Edge to DOUT tEN 5 30 ns enabled DOUT Access Time after SCLK tDACC 17 27 ns Falling Edge DOUT Hold Time after SCLK tDHLD 4 ns Falling Edge DIN Set-up Time prior to SCLK tDS 10 3 ns Rising Edge DIN Hold Time after SCLK tDH 10 3 ns Rising Edge tCH SCLK High Time 0.4 × tSCLK ns tCL SCLK Low Time 0.4 × tSCLK ns DOUT falling 2.4 20 ns CS Rising Edge to DOUT High- tDIS Impedance DOUT rising 0.9 20 ns (1) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level). Figure 1. ADC128S052 Operational Timing Diagram Figure 2. ADC128S052 Serial Timing Diagram 8 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: ADC128S052 ADC128S052-Q1 |
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