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ADS4249IRGCT Datasheet(PDF) 7 Page - Texas Instruments

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No. de pieza ADS4249IRGCT
Descripción Electrónicos  Dual-Channel, 14-Bit, 250-MSPS Ultralow-Power ADC
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Fabricante Electrónico  TI1 [Texas Instruments]
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ADS4249IRGCT Datasheet(HTML) 7 Page - Texas Instruments

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ADS4249
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SBAS534E – JULY 2011 – REVISED JANUARY 2016
Pin Functions (LVDS Mode) (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
38
39
NC
Do not connect, must be floated
58
59
Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized
through a hardware RESET by applying a high pulse on this pin or by using the
RESET
12
I
software reset option; see the Serial Interface Configuration section.
In parallel interface mode, the RESET pin must be permanently tied high.
SCLK and SEN are used as parallel control pins in this mode. This pin has an
internal 150-k
Ω pull-down resistor.
This pin functions as a serial interface clock input when RESET is low. SCLK
SCLK
13
I
controls the low-speed mode selection when RESET is tied high; see Table 7
for detailed information. This pin has an internal 150-k
Ω pull-down resistor.
SDATA
14
I
Serial interface data input; this pin has an internal 150-k
Ω pull-down resistor.
This pin functions as a serial interface register readout when the READOUT bit
SDOUT
64
O
is enabled. When READOUT = 0, this pin is put into a high-impedance state.
This pin functions as a serial interface enable input when RESET is low. SEN
controls the output interface and data format selection when RESET is tied
SEN
15
I
high; see Table 8 for detailed information. This pin has an internal 150-k
Ω pull-
up resistor to AVDD.
This pin outputs the common-mode voltage (0.95 V) that can be used
VCM
23
O
externally to bias the analog input pins
Copyright © 2011–2016, Texas Instruments Incorporated
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