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ADS4145IRGZR Datasheet(PDF) 4 Page - Texas Instruments |
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ADS4145IRGZR Datasheet(HTML) 4 Page - Texas Instruments |
4 / 74 page 36 35 34 33 32 31 30 29 28 27 26 25 12 11 10 9 8 7 6 5 4 3 2 1 DRGND DRVDD NC NC NC NC RESET SCLK SDATA SEN AVDD AGND DRGND DRVDD OVR_SDOUT CLKOUTM CLKOUTP DFS OE AVDD AGND CLKP CLKM AGND Thermal Pad 36 35 34 33 32 31 30 29 28 27 26 25 12 11 10 9 8 7 6 5 4 3 2 1 DRGND DRVDD D0_D1_P D0_D1_M NC NC RESET SCLK SDATA SEN AVDD AGND DRGND DRVDD OVR_SDOUT CLKOUTM CLKOUTP DFS OE AVDD AGND CLKP CLKM AGND Thermal Pad 4 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520B – FEBRUARY 2011 – REVISED JANUARY 2016 www.ti.com Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated 6 Pin Configuration and Functions ADS412x RGZ Package 48-Pin VQFN With Exposed Thermal Pad LVDS Mode - Top View ADS414x RGZ Package 48-Pin VQFN With Exposed Thermal Pad LVDS Mode - Top View The thermal pad is connected to DRGND. Pin Functions - LVDS Mode PIN I/O DESCRIPTION NAME ADS412x ADS414x AGND 9, 12, 14, 17, 19, 25 9, 12, 14, 17, 19, 25 I Analog ground AVDD 8, 18, 20, 22, 24, 26 8, 18, 20, 22, 24, 26 I 1.8-V analog power supply CLKM 11 11 I Differential clock input, complement CLKP 10 10 I Differential clock input, true CLKOUTM 4 4 O Differential output clock, complement CLKOUTP 5 5 O Differential output clock, true D0_D1_M 37 33 O Differential output data D0 and D1 multiplexed, complement D0_D1_P 38 34 O Differential output data D0 and D1 multiplexed, true D2_D3_M 39 37 O Differential output data D2 and D3 multiplexed, complement D2_D3_P 40 38 O Differential output data D2 and D3 multiplexed, true D4_D5_M 41 39 O Differential output data D4 and D5 multiplexed, complement D4_D5_P 42 40 O Differential output data D4 and D5 multiplexed, true D6_D7_M 43 41 O Differential output data D6 and D7 multiplexed, complement D6_D7_P 44 42 O Differential output data D6 and D7 multiplexed, true D8_D9_M 45 43 O Differential output data D8 and D9 multiplexed, complement D8_D9_P 46 44 O Differential output data D8 and D9 multiplexed, true D10_D11_M 47 45 O Differential output data D10 and D11 multiplexed, complement D10_D11_P 48 46 O Differential output data D10 and D11 multiplexed, true D12_D13_M — 47 O Differential output data D12 and D13 multiplexed, complement D12_D13_P — 48 O Differential output data D12 and D13 multiplexed, true DFS 6 6 I Data format select input. This pin sets the DATA FORMAT (twos complement or offset binary) and the LVDS/CMOS output interface type. See Table 4 for detailed information. DRGND 1, 36, PAD 1, 36, PAD I Digital and output buffer ground DRVDD 2, 35 2, 35 I 1.8-V digital and output buffer supply INM 16 16 I Differential analog input, negative INP 15 15 I Differential analog input, positive |
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