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ADS8556 Datasheet(PDF) 6 Page - Texas Instruments |
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ADS8556 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 47 page  6 ADS8556, ADS8557, ADS8558 SBAS404D – OCTOBER 2006 – REVISED FEBRUARY 2016 www.ti.com Product Folder Links: ADS8556 ADS8557 ADS8558 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. PARALLEL INTERFACE (PAR/SER = 0) SERIAL INTERFACE (PAR/SER = 1) AVDD 26, 34, 35, 40, 41, 46, 47, 50, 60 P Analog power supply (4.5 V to 5.5 V). Decouple each pin with a 100-nF ceramic capacitor to AGND. Use an additional 10- μF capacitor to AGND close to the device but without compromising the placement of the smaller capacitor. Pin 26 can have a dedicated power supply if the difference between its potential and AVDD is always kept within ±300 mV. RANGE/XCLK 27 DI, DIO Hardware mode (HW/SW = 0): Input voltage range select input. When low, the analog input range is ±4 VREF. When high, the analog input range is ±2 VREF. Software mode (HW/SW = 1): External conversion clock input, if CR bit C11 (CLKSEL) is set high or internal conversion clock output, if CR bit C10 (CLKOUT_EN) is set high. If not used, connect to BVDD or BGND. RESET 28 DI Reset input, active high. Aborts any ongoing conversions. Resets the internal control register to 0x000003FF. The RESET pulse must be at least 50 ns long. WORD/BYTE 29 DI Output mode selection input. When low, data are transferred in word mode using DB[15:0]. When high, data are transferred in byte mode using DB[15:8] with the byte order controlled by HBEN pin while two accesses are required for a complete 16-bit transfer. Connect to BGND. HVSS 30 P Negative supply voltage for the analog inputs (–16.5 V to –5 V). Decouple with a 100-nF ceramic capacitor to AGND placed next to the device and a 10- μF capacitor to AGND close to the device but without compromising the placement of the smaller capacitor. HVDD 31 P Positive supply voltage for the analog inputs (5 V to 16.5 V). Decouple with a 100-nF ceramic capacitor to AGND placed next to the device and a 10- μF capacitor to AGND close to the device but without compromising the placement of the smaller capacitor. CH_A0 33 AI Analog input of channel A0. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C26 (RANGE_A) in software mode. CH_A1 36 AI Analog input of channel A1. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C26 (RANGE_A) in software mode. CH_B0 39 AI Analog input of channel B0. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C27 (RANGE_B) in software mode. CH_B1 42 AI Analog input of channel B1. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C27 (RANGE_B) in software mode. CH_C0 45 AI Analog input of channel C0. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C28 (RANGE_C) in software mode. CH_C1 48 AI Analog input of channel C1. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C28 (RANGE_C) in software mode. REFIO 51 AIO Reference voltage input/output (0.5 V to 3.025 V). The internal reference is enabled via REFEN/WR pin in hardware mode or CR bit C25 (REFEN) in software mode. The output value is controlled by the internal DAC (CR bits C[9:0]). Connect a 470-nF ceramic decoupling capacitor between this pin and pin 52. REFC_A 54 AI Decoupling capacitor for reference of channels A. Connect a 10- μF ceramic decoupling capacitor between this pin and pin 53. REFC_B 56 AI Decoupling capacitor for reference of channels B. Connect a 10- μF ceramic decoupling capacitor between this pin and pin 55. REFC_C 58 AI Decoupling capacitor for reference of channels C. Connect a 10- μF ceramic decoupling capacitor between this pin and pin 57. PAR/SER 61 DI Interface mode selection input. When low, the parallel interface is selected. When high, the serial interface is enabled. HW/SW 62 DI Mode selection input. When low, the hardware mode is selected and part works according to the settings of external pins. When high, the software mode is selected in which the device is configured by writing into the control register. |
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