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ADS8528SRGCR Datasheet(PDF) 7 Page - Texas Instruments |
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ADS8528SRGCR Datasheet(HTML) 7 Page - Texas Instruments |
7 / 57 page 7 ADS8528, ADS8548, ADS8568 www.ti.com SBAS543C – AUGUST 2011 – REVISED FEBRUARY 2016 Product Folder Links: ADS8528 ADS8548 ADS8568 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. PARALLEL INTERFACE (PAR/SER = 0) SERIAL INTERFACE (PAR/SER = 1) DB4 29 DIO Data bit 4 input/output Connect to DGND DB5/SEL_CD 28 DIO, DI Data bit 5 input/output Select SDO_C and SDO_D input. When high, data from channel pair C are available on SDO_C and data from channel pair D are available on SDO_D. When low and SEL_B = 1, data from channel pairs A and C are available on SDO_A and data from channel pairs B and D are available on SDO_B. When low and SEL_B = 0, data from all eight channels are available on SDO_A. DB6/SEL_B 27 DIO, DI Data bit 6 input/output Select SDO_B input. When low, SDO_B is disabled and data from all eight channels are only available through SDO_A. When high and SEL_CD = 0, data from channel pairs B and D are available on SDO_B. When SEL_CD = 1, data from channel pair B are available on SDO_B. DB7 26 DIO Data bit 7 input/output Must be connected to DGND DB8/DCEN 23 DIO, DI Data bit 8 input/output Daisy-chain enable input. When high, DB[3:0] serve as daisy-chain inputs DCIN_[A:D]. If daisy-chain mode is not used, connect to DGND. DB9/SDI 22 DIO, DI Data bit 9 input/output Hardware mode (HW/SW = 0): connect to DGND. Software mode (HW/SW = 1): serial data input. DB10/SCLK 21 DIO, DI Data bit 10 input/output Serial interface clock input. DB11/ REFBUFEN 20 DIO, DI Data bit 11 input/output. Output is MSB for the ADS8528. Hardware mode (HW/SW = 0): reference buffer enable input. When low, all internal reference buffers are enabled (mandatory if internal reference is used). When high, all reference buffers are disabled. Software mode (HW/SW = 1): connect to DGND or DVDD. The internal reference buffers are controlled by CONFIG bit C14 (REFBUFEN). DB12/SDO_A 19 DIO, DO Data bit 12 input/output. Output is sign extension for the ADS8528. Data output for channel pair A. When SEL_CD = 0, data from channel pair C are also available on this output. When SEL_CD = 0 and SEL_B = 0, SDO_A functions as single data output for all eight channels. DB13/SDO_B 18 DIO, DO Data bit 13 input/output. Output is sign extension for the ADS8528 and MSB for the ADS8548. When SEL_B = 1, this pin is the data output for channel pair B. When SEL_B = 0, tie this pin to DGND. When SEL_CD = 0, data from channel pair D are also available on this output. DB14/SDO_C 17 DIO, DO Data bit 14 input/output. Output is sign extension for the ADS8528 and ADS8548. When SEL_CD = 1, this pin is the data output for channel pair C. When SEL_CD = 0, tie this pin to DGND. DB15/SDO_D 16 DIO, DO Data bit 15 (MSB) input/output. Output is sign extension for the ADS8528 and ADS8548. When SEL_CD = 1, this pin is the data output for channel pair D. When SEL_CD = 0, tie this pin to DGND. DGND 24 P Buffer I/O ground, connect to digital ground plane DVDD 25 P Buffer I/O supply, connect to digital supply. Decouple according to the Power Supply Recommendations section. HVDD 48 P Positive supply voltage for the analog inputs. Decouple according to the Power Supply Recommendations section. HVSS 1 P Negative supply voltage for the analog inputs. Decouple according to the Power Supply Recommendations section. HW/SW 41 DI Mode selection input. When low, hardware mode is selected and the device functions according to the settings of the external pins. When high, software mode is selected and the device is configured by writing to the Configuration register (CONFIG). PAR/SER 8 DI Interface mode selection input. When low, the parallel interface is selected. When high, the serial interface is enabled. RANGE/XCLK 34 DI/DI/DO Hardware mode (HW/SW = 0): analog input voltage range select input. When low, the analog input voltage range is ±4 VREF. When high, the analog input voltage range is ±2 VREF. Software mode (HW/SW = 1): this pin is an external conversion clock input if CONFIG bit C29 = 1 (CLKSEL); or an internal conversion clock output if CONFIG bit C28 = 1 (CLKOUT_EN). If this pin is not used, connect to DGND. RD 12 DI/DI Read data input. When low, the parallel data output is enabled (if CS = 0). When high, the data output is disabled. Must be connected to DGND. |
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