CLK

1

16

CS

SDI

DB13

t

DH

t

CL

t

CH

t

CSH

t

DS

t

CSS

DB1

DB0

DB15

DB14

7

DAC8811

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SLAS411D – NOVEMBER 2004 – REVISED FEBRUARY 2016

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(1)

Specified by design and characterization; not production tested.

(2)

All ac characteristic tests are performed in a closed-loop system using the THS4011 I-to-V converter amplifier.

7.6 Timing Requirements

MIN

NOM

MAX

UNIT

INTERFACE TIMING

Clock input frequency

50

MHz

Clock pulse width high

10

ns

Clock pulse width low

10

ns

CS to Clock setup time

0

ns

Clock to CS hold time

10

ns

Data setup time

5

ns

Data hold time

10

ns

Output voltage settling time

To ±0.1% of full-scale, Data = 0000h to

FFFFh to 0000h

0.3

µs

To ±0.0015% of full-scale, Data = 0000h

to FFFFh to 0000h

0.5

µs

Figure 1. DAC8811 Timing Diagram