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DLPC3438CZEZ Datasheet(PDF) 9 Page - Texas Instruments |
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DLPC3438CZEZ Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 62 page  DLPC3433, DLPC3438 www.ti.com DLPS035B – FEBRUARY 2014 – REVISED JANUARY 2016 Pin Functions – DMD Reset and Bias Control PIN I/O DESCRIPTION NAME NUMBER DMD driver enable (active high)/ DMD reset (active low). Assuming the corresponding I/O power is supplied, this signal will be driven low after the DMD is parked and before power is removed from the DMD. If the 1.8-V power to the DMD_DEN_ARSTZ B1 O2 DLPC343x is independent of the 1.8-V power to the DMD, then TI recommends a weak, external pulldown resistor to hold the signal low in the event DLPC343x power is inactive while DMD power is applied. DMD_LS_CLK A1 O3 DMD, low speed interface clock DMD_LS_WDATA A2 O3 DMD, low speed serial write data DMD_LS_RDATA B2 I6 DMD, low speed serial read data Pin Functions – DMD Sub-LVDS Interface PIN I/O DESCRIPTION NAME NUMBER DMD_HS_CLK_P A7 O4 DMD high speed interface DMD_HS_CLK_N B7 DMD_HS_WDATA_H_P A3 DMD_HS_WDATA_H_N B3 DMD_HS_WDATA_G_P A4 DMD_HS_WDATA_G_N B4 DMD_HS_WDATA_F_P A5 DMD_HS_WDATA_F_N B5 DMD_HS_WDATA_E_P A6 DMD_HS_WDATA_E_N B6 DMD high speed interface lanes, write data bits: (The true numbering and O4 DMD_HS_WDATA_D_P A8 application of the DMD_HS_DATA pins are software configuration dependent) DMD_HS_WDATA_D_N B8 DMD_HS_WDATA_C_P A9 DMD_HS_WDATA_C_N B9 DMD_HS_WDATA_B_P A10 DMD_HS_WDATA_B_N B10 DMD_HS_WDATA_A_P A11 DMD_HS_WDATA_A_N B11 Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: DLPC3433 DLPC3438 |
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