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DLPC6401ZFF Datasheet(PDF) 2 Page - Texas Instruments |
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DLPC6401ZFF Datasheet(HTML) 2 Page - Texas Instruments |
2 / 50 page DLPC6401 DLPS031C – DECEMBER 2013 – REVISED AUGUST 2015 www.ti.com Table of Contents 1 Features .................................................................. 1 7 Detailed Description ............................................ 22 7.1 Overview ................................................................. 22 2 Applications ........................................................... 1 7.2 Functional Block Diagram ....................................... 22 3 Description ............................................................. 1 7.3 Feature Description................................................. 23 4 Revision History..................................................... 2 7.4 Device Functional Modes........................................ 28 5 Pin Configuration and Functions ......................... 3 8 Application and Implementation ........................ 29 6 Specifications....................................................... 11 8.1 Application Information............................................ 29 6.1 Absolute Maximum Ratings .................................... 11 8.2 Typical Application ................................................. 29 6.2 ESD Ratings............................................................ 11 9 Power Supply Recommendations ...................... 32 6.3 Recommended Operating Conditions ..................... 12 9.1 System Power Regulation ...................................... 32 6.4 Thermal Information ................................................ 12 9.2 System Power-Up Sequence .................................. 32 6.5 Electrical Characteristics......................................... 13 9.3 Power-On Sense (POSENSE) Support .................. 33 6.6 Electrical Characteristics (Normal Mode)................ 14 9.4 System Environment and Defaults.......................... 33 6.7 System Oscillators Timing Requirements ............... 14 10 Layout................................................................... 35 6.8 Test and Reset Timing Requirements .................... 15 10.1 Layout Guidelines ................................................. 35 6.9 JTAG Interface: I/O Boundary Scan Application Timing Requirements ............................................... 15 10.2 Layout Example .................................................... 41 6.10 Port 1 Input Pixel Interface Timing Requirements 16 10.3 Thermal Considerations ........................................ 42 6.11 Port 2 Input Pixel Interface (FPD-Link Compatible 11 Device and Documentation Support ................. 44 LVDS Input) Timing Requirements .......................... 16 11.1 Device Support...................................................... 44 6.12 Synchronous Serial Port (SSP) Interface Timing 11.2 Community Resources.......................................... 46 Requirements........................................................... 17 11.3 Trademarks ........................................................... 46 6.13 Programmable Output Clocks Switching 11.4 Electrostatic Discharge Caution ............................ 46 Characteristics ......................................................... 17 11.5 Glossary ................................................................ 46 6.14 Synchronous Serial Port (SSP) Interface Switching 12 Mechanical, Packaging, and Orderable Characteristics ......................................................... 18 Information ........................................................... 46 6.15 JTAG Interface: I/O Boundary Scan Application Switching Characteristics ......................................... 18 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (June 2015) to Revision C Page • Updated the Device Markings graphic.................................................................................................................................. 45 Changes from Revision A (January 2014) to Revision B Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 • Removed V(ESD) values from Electrical Characteristics table .............................................................................................. 13 Changes from Original (December 2013) to Revision A Page • Removed product preview banner.......................................................................................................................................... 1 2 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: DLPC6401 |
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