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ADS7041IDCUT Datasheet(PDF) 7 Page - Texas Instruments |
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ADS7041IDCUT Datasheet(HTML) 7 Page - Texas Instruments |
7 / 42 page 1 2 3 4 5 6 7 8 9 10 SCLK CS tSU_CSCK tDV_CSDO tD_CKDO tDZ_CSDO Sample N Sample N+1 tACQ tCONV tCYCLE tPH_CS 0 0 SDO Data for Sample N tPH_CK tPL_CK tD_CKCS tSCLK D9 D8 D7 D6 D5 D4 D3 D2 11 12 D1 D0 ADS7041 www.ti.com SBAS675C – NOVEMBER 2014 – REVISED DECEMBER 2015 6.6 Timing Characteristics All specifications are at TA = –40°C to 125°C, AVDD = 1.65 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and CLOAD on SDO = 20 pF, unless otherwise specified. MIN TYP MAX UNIT TIMING SPECIFICATIONS fTHROUGHPUT Throughput 1 MSPS tCYCLE Cycle time 1 µs tCONV Conversion time 10.5 × tSCLK + tSU_CSCK ns tDV_CSDO Delay time: CS falling to data enable 10 ns Delay time: SCLK falling to (next) data valid on DOUT, 30 ns AVDD = 1.8 V to 3.6 V tD_CKDO Delay time: SCLK falling to (next) data valid on DOUT, 50 ns AVDD = 1.65 V to 1.8 V tDZ_CSDO Delay time: CS rising to DOUT going to 3-state 5 ns TIMING REQUIREMENTS tACQ Acquisition time 235 ns fSCLK SCLK frequency 0.016 14 MHz tSCLK SCLK period 71.43 ns tPH_CK SCLK high time 0.45 0.55 tSCLK tPL_CK SCLK low time 0.45 0.55 tSCLK tPH_CS CS high time 60 ns tSU_CSCK Setup time: CS falling to SCLK falling 15 ns tD_CKCS Delay time: last SCLK falling to CS rising 10 ns Figure 1. Timing Diagram Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ADS7041 |
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