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ADC12D1600RFIUT/NOPB Datasheet(PDF) 7 Page - Texas Instruments |
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ADC12D1600RFIUT/NOPB Datasheet(HTML) 7 Page - Texas Instruments |
7 / 84 page 50k VA AGND VA AGND 50k Control from VCMO VCMO 100 GND VA 200k 8 pF VCMO Enable AC Coupling VA GND ADC12D1000RF, ADC12D1600RF www.ti.com SNAS519H – JULY 2011 – REVISED AUGUST 2015 Table 3-1. Analog Front-End and Clock Balls (continued) PIN I/O EQUIVALENT CIRCUIT DESCRIPTION NAME NO. Bandgap Voltage Output or LVDS Common-mode Voltage Select. This pin provides a buffered version of the bandgap output voltage and is capable of sourcing or sinking 100 µA and driving a VBG B1 O load of up to 80 pF. Alternately, this pin may be used to select the LVDS digital output common-mode voltage. If tied to logic-high, the 1.2-V LVDS common- mode voltage is selected; 0.8 V is the default. Common-Mode Voltage Output or Signal Coupling Select. If AC-coupled operation at the analog inputs is desired, this pin should be held at logic-low level. This pin is capable of sourcing or sinking up to 100 µA. For DC-coupled operation, this VCMO C2 I/O pin should be left floating or terminated into high impedance. In DC-coupled Mode, this pin provides an output voltage which is the optimal common-mode voltage for the input signal and should be used to set the common-mode voltage of the driving buffer. Differential signal I- and Q-inputs. In the Non-Dual Edge Sampling (Non-DES) Mode, each I- and Q-input is sampled and converted by its respective channel with each positive transition of the CLK input. In Non-ECM (Non-Extended Control Mode) and DES Mode, both channels sample the I-input. In Extended Control Mode (ECM), the Q-input may optionally be selected for conversion in DES Mode by the DEQ Bit (Addr: 0h, Bit 6). Each I- and Q-channel input has an internal common-mode bias that is disabled when DC-coupled Mode is VinI+/- H1/J1 I selected. Both inputs must be either AC- VinQ+/- N1/M1 or DC-coupled. The coupling mode is selected by the VCMO Pin. In Non-ECM, the full-scale range of these inputs is determined by the FSR Pin; both I- and Q-channels have the same full-scale input range. In ECM, the full- scale input range of the I- and Q-channel inputs may be independently set through the Control Register (Addr: 3h and Addr: Bh). The high and low full-scale input range setting in Non-ECM corresponds to the mid and minimum full-scale input range in ECM. The input offset may also be adjusted in ECM. Copyright © 2011–2015, Texas Instruments Incorporated Pin Configuration and Functions 7 Submit Documentation Feedback Product Folder Links: ADC12D1000RF ADC12D1600RF |
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