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ADC0802LCWM Datasheet(PDF) 6 Page - Texas Instruments |
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ADC0802LCWM Datasheet(HTML) 6 Page - Texas Instruments |
6 / 56 page ADC0801, ADC0802, ADC0803, ADC0804, ADC0805 SNOSBI1C – NOVEMBER 2009 – REVISED JUNE 2015 www.ti.com AC Electrical Characteristics (continued) The following specifications apply for VCC=5 VDC and TMIN≤ TA≤TMAX (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tW(WR) Width of WR Input (Start Pulse Width) CS = 0 VDC (3) 100 L Access Time (Delay from Falling Edge of RD to tACC CL = 100 pF 135 200 Output Data Valid) ns t1H, Tri-State Control (Delay from Rising Edge of RD CL = 10 pF, RL = 10k (See Tri-State 125 200 t0H to Hi-Z State) Test Circuits and Waveforms) Delay from Falling Edge of WR or RD to Reset tWI, tRI 300 450 of INTR CIN Input Capacitance of Logic Control Inputs 5 7.5 pF COUT Tri-State Output Capacitance (Data Buffers) 5 7.5 CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately] VIN (1) Logical “1” Input Voltage (Except Pin 4 CLK IN) VCC = 5.25 VDC 2 15 VDC VIN (0) Logical “0” Input Voltage (Except Pin 4 CLK IN) VCC = 4.75 VDC 0.8 IIN (1) Logical “1” Input Current (All Inputs) VIN = 5 VDC 0.005 1 µADC IIN (0) Logical “0” Input Current (All Inputs) VIN = 0 VDC –1 –0.005 CLOCK IN AND CLOCK R VT+ CLK IN (Pin 4) Positive Going Threshold Voltage 2.7 3.1 3.5 CLK IN (Pin 4) Negative Going Threshold VT− 1.5 1.8 2.1 Voltage VH CLK IN (Pin 4) Hysteresis (VT+)–(VT−) 0.6 1.3 2 VDC VOUT Logical “0” CLK R Output Voltage IO = 360 µA, VCC = 4.75 VDC 0.4 (0) VOUT Logical “1” CLK R Output Voltage IO = −360 µA, VCC = 4.75 VDC 2.4 (1) DATA OUTPUTS AND INTR Data Outputs IOUT = 1.6 mA, VCC = 4.75 VDC 0.4 VOUT Logical “0” Output (0) Voltage INTR Output IOUT = 1.0 mA, VCC = 4.75 VDC 0.4 VDC IO = −360 µA, VCC = 4.75 VDC 2.4 VOUT Logical “1” Output Voltage (1) IO = −10 µA, VCC = 4.75 VDC 4.5 VOUT = 0 VDC –3 Tri-State Disabled Output Leakage (All Data IOUT µADC Buffers) VOUT = 5 VDC 3 ISOURC VOUT Short to GND, TA = 2 5°C 4.5 6 E mADC ISINK VOUT Short to VCC, TA = 25°C 9 16 POWER SUPPLY Supply Current ADC0801/02/03/04LCJ/05 1.1 1.8 fCLK = 640 kHz, VREF/2 = NC, ICC (Includes Ladder mA TA = 25°C and CS = 5 V ADC0804LCN/LCWM 1.9 2.5 Current) (3) The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse. 6 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 |
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