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ADS1263IPW Datasheet(PDF) 8 Page - Texas Instruments

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No. de pieza ADS1263IPW
Descripción Electrónicos  32-Bit, Precision, 38-kSPS, Analog-to-Digital Converter (ADC)
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

ADS1263IPW Datasheet(HTML) 8 Page - Texas Instruments

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ADS1262, ADS1263
SBAS661B – FEBRUARY 2015 – REVISED JULY 2015
www.ti.com
7.5 Electrical Characteristics
Minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications are at TA = 25°C.
All specifications are at VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz, ADC1 data rate = 20 SPS
with PGA enabled and gain = 1, and ADC2 data rate = 10 SPS with gain = 1 (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC1 ANALOG INPUTS
Gain = 32
2
nA
Absolute input current
PGA bypassed
150
nA
Gain = 32
0.1
nA
Differential input current
PGA bypassed, VIN = 5 V
150
nA
PGA enabled
1
G
Ω
Differential input impedance
PGA bypassed
40
M
Ω
Channel-to-channel crosstalk
DC, VAVSS ≤ VINX ≤ VAVDD
0.5
µV/V
ADC1 PERFORMANCE
PGA gain
1, 2, 4, 8, 16, 32
V/V
Resolution
32
Bits
DR
Data rate
2.5
38400
SPS
Noise performance
See Table 1
INL
Integral nonlinearity
Gain = 1 to 32, PGA bypassed
3
12
ppm
Chop mode off
350 / Gain
800 / Gain
µV
TA = 25°C
VOS
Offset voltage
Chop mode on
±0.1 / Gain
±0.5 / Gain
µV
After calibration(1)
Noise / 4
Chop mode off
30 / Gain + 10
100 / Gain + 50
nV/°C
Offset voltage drift
Chop mode on
1
5
nV/°C
TA = 25°C, gain = 1 to 32
±50
±300
ppm
GE
Gain error
After calibration(1)
Noise / 4
Gain drift
Gain = 1 to 32, and PGA bypassed
0.5
4
ppm/°C
NMRR
Normal-mode rejection ratio(2)
See Table 11
fIN = 60 Hz, data rate = 20 SPS
130
dB
CMRR
Common-mode rejection ratio(3)
fIN = 60 Hz, data rate = 400 SPS
100
120
dB
AVDD and AVSS
80
90
dB
PSRR
Power-supply rejection ratio(4)
DVDD
80
120
dB
ADC2 ANALOG INPUTS (ADS1263)
Absolute input current
Gain = 16
2
nA
Differential input current
Gain = 16
0.5
nA
ADC2 PERFORMANCE (ADS1263)
Gain
1, 2, 4, 8, 16, 32, 64, 128
V/V
Resolution
24
Bits
DR
Data rate
10, 100, 400, 800
SPS
Noise performance
See Table 3
Gain = 1 to 64
4
20
ppm
INL
Integral nonlinearity
Gain = 128
7
30
ppm
VOS
Offset voltage
TA = 25°C, gain = 1 to 128
±150
±500
µV
Offset voltage drift
Gain = 1 to 128
30
200
nV/°C
GE
Gain error
TA = 25°C, gain = 1 to 128
±500
±3000
ppm
Gain drift
Gain = 1 to 128
1
5
ppm/°C
NMRR
Normal-mode rejection ratio
See Table 15
fIN = 60 Hz, DR = 10 SPS
110
dB
CMRR
Common-mode rejection ratio
fIN = 60 Hz, DR = 400 SPS, gain = 8
75
90
dB
PSRR
Power-supply rejection ratio
AVDD and AVSS
75
90
dB
(1)
Offset and gain calibration accuracy on the order of ADC conversion noise/4. Conversion noise depends on data rate and PGA gain.
(2)
Normal-mode rejection ratio depends on the digital filter setting.
(3)
Common-mode rejection ratio is specified at date rate 20 SPS and 400 SPS.
(4)
Power-supply rejection ratio is specified at dc.
8
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