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ADS8698IDBTR Datasheet(PDF) 10 Page - Texas Instruments

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No. de pieza ADS8698IDBTR
Descripción Electrónicos  4- and 8-Channel, Single-Supply, SAR ADCs
Download  77 Pages
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

ADS8698IDBTR Datasheet(HTML) 10 Page - Texas Instruments

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1
2
14
15
16
17
25
26
27
28
29
30
31
32
SCLK
CS
D9
#2
D8
#2
D7
#2
D6
#2
D5
#2
D4
#2
SDO
tSU_CSCK
tDV_CSDO
tHT_CKDO
tSU_DOCK
tDZ_CSDO
Sample
N
Sample
N + 1
tACQ
tCONV
tS
Data from sample N
tPH_CS
33
34
D17
#2
D16
#2
18
D3
#2
D2
#2
D1
#2
D0
#2
B15
B14
B2
B1
B0
X
X
X
X
X
X
SDI
X
X
X
X
X
X
tPH_CK
tPL_CK
tSCLK
tSU_DICK
tHT_CKDI
tD_CKCS
7
8
9
B9
B8
B7
B10
B3
D9
#1
D8
#1
D7
#1
D6
#1
D5
#1
D4
#1
DAISY
D17
#1
D16
#1
D3
#1
D2
#1
D1
#1
D0
#1
tHT_CKDSY
tSU_DSYCK
ADS8694, ADS8698
SBAS686 – JULY 2015
www.ti.com
7.6 Timing Requirements: Serial Interface
Minimum and maximum specifications are at TA = –40°C to 125°C. Typical specifications are at TA = 25°C.
AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), SDO load = 20 pF, and fSAMPLE = 500 kSPS, unless otherwise noted.
MIN
TYP
MAX
UNIT
TIMING SPECIFICATIONS
fS
Sampling frequency (fCLK = max)
500
kSPS
tS
ADC cycle time period (fCLK = max)
2
µs
fSCLK
Serial clock frequency (fS = max)
18
MHz
tSCLK
Serial clock time period (fS = max)
56
ns
tCONV
Conversion time
825
ns
tDZ_CSDO
Delay time: CS falling to data enable
10
ns
tD_CKCS
Delay time: last SCLK falling to CS rising
10
ns
tDZ_CSDO
Delay time: CS rising to SDO going to 3-state
10
ns
TIMING REQUIREMENTS
tACQ
Acquisition time
1175
ns
tPH_CK
Clock high time
0.4
0.6
tSCLK
tPL_CK
Clock low time
0.4
0.6
tSCLK
tPH_CS
CS high time
30
ns
tSU_CSCK
Setup time: CS falling to SCLK falling
30
ns
tHT_CKDO
Hold time: SCLK falling to (previous) data valid on SDO
10
ns
tSU_DOCK
Setup time: SDO data valid to SCLK falling
25
ns
tSU_DICK
Setup time: SDI data valid to SCLK falling
5
ns
tHT_CKDI
Hold time: SCLK falling to (previous) data valid on SDI
5
ns
tSU_DSYCK
Setup time: DAISY data valid to SCLK falling
5
ns
tHT_CKDSY
Hold time: SCLK falling to (previous) data valid on DAISY
5
ns
Figure 1. Serial Interface Timing Diagram
10
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Product Folder Links: ADS8694 ADS8698


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