GS1661 datasheet(5/84 Pages) SEMTECH

No. de pieza	GS1661

Descripción Electrónicos	HD/SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Video Processing

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Fabricante Electrónico	SEMTECH [Semtech Corporation]

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5 / 84 page

GS1661 HD/SD SDI Receiver

Data Sheet

53751 - 3

September 2012

5 of 84

List of Figures

Figure 3-1: Digital Input Pin with Schmitt Trigger............................................................................... 20

Figure 3-2: Bidirectional Digital Input/Output Pin..............................................................................20

Figure 3-3: Bidirectional Digital Input/Output Pin with programmable drive strength ........ 21

Figure 3-4: XTAL1/XTAL2/XTAL-OUT ................................................................................................... 21

Figure 3-5: VBG .............................................................................................................................................. 22

Figure 3-6: LB_CONT .................................................................................................................................... 22

Figure 3-7: Loop Filter .................................................................................................................................. 22

Figure 3-8: SDO/SDO .................................................................................................................................... 23

Figure 3-9: Equalizer Input Equivalent Circuit .................................................................................... 23

Figure 4-1: GS1661 Integrated EQ Block Diagram ............................................................................. 25

Figure 4-2: 27MHz Clock Sources ............................................................................................................ 28

Figure 4-3: PCLK to Data and Control Signal Output Timing - SDR Mode 1 .............................. 31

Figure 4-4: PCLK to Data and Control Signal Output Timing - SDR Mode 2 .............................. 32

Figure 4-5: Switch Line Locking on a Non-Standard Switch Line ................................................. 36

Figure 4-6: H:V:F Output Timing - HDTV 20-bit Mode ..................................................................... 39

Figure 4-7: H:V:F Output Timing - HDTV 10-bit Mode ..................................................................... 39

Figure 4-8: H:V:F Output Timing - HD 20-bit Output Mode ............................................................ 40

Figure 4-9: H:V:F Output Timing - HD 10-bit Output Mode ............................................................ 40

Figure 4-10: H:V:F Output Timing - SD 20-bit Output Mode .......................................................... 40

Figure 4-11: H:V:F Output Timing - SD 10-bit Output Mode .......................................................... 40

Figure 4-12: H:V:DE Output Timing 1280 x 720p @ 59.94/60 (Format 4) ................................... 42

Figure 4-13: H:V:DE Output Timing 1920 x 1080i @ 59.94/60 (Format 5) ................................. 42

Figure 4-14: H:V:DE Output Timing 720 (1440) x 480i @ 59.94/60 (Format 6&7) .................... 43

Figure 4-15: H:V:DE Output Timing 1280 x 720p @ 50 (Format 19) ............................................. 43

Figure 4-16: H:V:DE Output Timing 1920 x 1080i @ 50 (Format 20) ........................................... 44

Figure 4-17: H:V:DE Output Timing 720 (1440) x 576 @ 50 (Format 21 & 22) ........................... 45

Figure 4-18: H:V:DE Output Timing 1920 x 1080p @ 23.94/24 (Format 32) .............................. 45

Figure 4-19: H:V:DE Output Timing 1920 x 1080p @ 25 (Format 33) .......................................... 46

Figure 4-20: H:V:DE Output Timing 1920 x 1080p @ 29.97/30 (Format 34) .............................. 46

Figure 4-21: Y/1ANC and C/2ANC Signal Timing .............................................................................. 54

Figure 4-22: Ancillary Data Extraction - Step A .................................................................................. 60

Figure 4-23: Ancillary Data Extraction - Step B ................................................................................... 61

Figure 4-24: Ancillary Data Extraction - Step C .................................................................................. 61

Figure 4-25: Ancillary Data Extraction - Step D .................................................................................. 62

Figure 4-26: GSPI Application Interface Connection ........................................................................ 63

Figure 4-27: Command Word Format ..................................................................................................... 64

Figure 4-28: Data Word Format ................................................................................................................ 64

Figure 4-29: Write Mode .............................................................................................................................. 65

Figure 4-30: Read Mode ............................................................................................................................... 65

Figure 4-31: GSPI Time Delay .................................................................................................................... 65

Figure 4-32: In-Circuit JTAG ...................................................................................................................... 76

Figure 4-33: System JTAG ........................................................................................................................... 76

Figure 4-34: Reset Pulse ............................................................................................................................... 77

Figure 7-1: Pb-free Solder Reflow Profile .............................................................................................. 83

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