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54FCT273DMQB Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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54FCT273DMQB Datasheet(HTML) 1 Page - National Semiconductor (TI) |
1 / 8 page 54FCT273 Octal D-Type Flip-Flop General Description The ’FCT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D in- put, one setup time before the LOW-to-HIGH clock transi- tion, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The de- vice is useful for applications where the true output only is re- quired and the Clock and Master Reset are common to all storage elements. Features n Eight edge-triggered D flip-flops n Buffered common clock n Buffered, asynchronous Master Reset n See ’FCT377 for clock enable version n See ’FCT373 for transparent latch version n See ’FCT374 for TRI-STATE® version n Output sink capability of 32 mA, source capability of 12 mA n TTL input and output level compatible n CMOS power consumption n Standard Microcircuit Drawing (SMD) 5962-8765601 Ordering Code Military Package Package Description Number 54FCT273DMQB J20A 20-Lead Ceramic Dual-In-Line 54FCT273FMQB W20A 20-Lead Cerpack 54FCT273LMQB E20A 20-Lead Ceramic Leadless Chip Carrier, Type C Connection Diagrams Pin Description Names D 0–D7 Data Inputs MR Master Reset (Active LOW) CP Clock Pulse Input (Active Rising Edge) Q 0–Q7 Data Outputs TRI-STATE® is a registered trademark of National Semiconductor Corporation. Pin Assignment for DIP and Flatpack DS100956-1 Pin Assignment for LCC DS100956-2 August 1998 © 1998 National Semiconductor Corporation DS100956 www.national.com |
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