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AD6649EBZ Datasheet(PDF) 1 Page - Analog Devices

No. de pieza AD6649EBZ
Descripción Electrónicos  IF Diversity Receiver
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Fabricante Electrónico  AD [Analog Devices]
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AD6649EBZ Datasheet(HTML) 1 Page - Analog Devices

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IF Diversity Receiver
Data Sheet
AD6649
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2011–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
FEATURES
SNR = 73.0 dBFS in a 95 MHz bandwidth at
185 MHz AIN and 245.76 MSPS
SFDR = 85 dBc at 185 MHz AIN and 250 MSPS
Noise density = −151.2 dBFS/Hz input at 185 MHz, −1 dBFS
AIN and 250 MSPS
Total power consumption: 1 W with fixed-frequency NCO,
95 MHz FIR filter
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Integrated dual-channel ADC
Sample rates of up to 250 MSPS
IF sampling frequencies to 400 MHz
Internal ADC voltage reference
Flexible input range
1.4 V p-p to 2.1 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Integrated wideband digital processor
32-bit complex numerically controlled oscillator (NCO)
FIR filter with 2 modes
Real output from an fS/4 output NCO
Amplitude detect bits for efficient AGC implementation
Energy saving power-down modes
Decimated, interleaved real LVDS data outputs
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMax, WCDMA,
CDMA2000, GSM, EDGE, LTE
General-purpose software radios
Broadband data applications
GENERAL DESCRIPTION
The AD6649 is a mixed-signal intermediate frequency (IF) receiver
consisting of dual 14-bit, 250 MSPS ADCs and a wideband digital
downconverter (DDC). The AD6649 is designed to support
communications applications, where low cost, small size, wide
bandwidth, and versatility are desired.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer is provided to
compensate for variations in the ADC clock duty cycle, allowing
the converters to maintain excellent performance.
FUNCTIONAL BLOCK DIAGRAM
DC
CORRECTION
ADC
THRESHOLD DETECT
AVDD
FDA
DRVDD
AD6649
VIN+A
VIN–A
FDB
DC
CORRECTION
REFERENCE
ADC
I
Q
Q
I
VIN–B
VIN+B
D13+/D13–
D0+/D0–
CLK+
CLK–
DCO+
DCO–
DIVIDE 1
TO 8
DUTY
CYCLE
STABILIZER
AGND
SDIO SCLK CSB
SPI
PROGRAMMING DATA
THRESHOLD DETECT
SELECTABLE
FIR
FILTER
SELECTABLE
FIR
FILTER
DIGITAL
INTERLEAVING
fS/4
NCO
OR+
OR–
OEB
PDWN
DCO
GENERATION
SYNC
MULTICHIP
SYNC
SELECTABLE
FIR
FILTER
SELECTABLE
FIR
FILTER
32-BIT
TUNING NCO
Figure 1.


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