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TPS65320-Q1 Datasheet(PDF) 7 Page - Texas Instruments |
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TPS65320-Q1 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 45 page  7 TPS65320-Q1 www.ti.com SLVSAY9F – DECEMBER 2012 – REVISED MARCH 2016 Product Folder Links: TPS65320-Q1 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Electrical Characteristics (continued) VI = 6 V to 27 V, EN1 = EN2 = VI, over-operating free-air temperature range TA = –40°C to +125°C and maximum operating junction temperature TJ = –40°C to +150°C, unless otherwise noted. VI is the voltage on the battery-supply pins, VIN and VIN_LDO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT COMP to switch-current transconductance 10.5 S Vref1 Voltage reference for FB1 pin Buck regulator output: 3.6 V to 10 V 0.788 0.8 0.812 V BUCK REGULATOR: CURRENT-LIMIT Current-limit threshold V(VIN) = 12 V, TJ = 25°C 4 6 A BUCK REGULATOR: TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) RT/CLK High threshold 1.9 2.2 V RT/CLK Low threshold 0.5 0.7 V BUCK REGULATOR: INTERNAL SOFT START TIMER IS(SS) Soft-start source current V(SS) = 0 V 1 2 4 μA LDO REGULATOR ΔVO(ΔVI) Line regulation V(VIN) = 6 V to 30 V, I(LDO_OUT) = 10 mA, V(LDO_OUT) = 3.3 V 20 mV ΔVO(ΔIL) Load regulation I(LDO_OUT) = 10 mA to 200 mA, V(VIN_LDO) = 14 V, V(LDO_OUT) = 3.3 V 35 mV VDROPOUT (V(VIN_LDO) – V(LDO_OUT)) Dropout voltage I(LDO_OUT) = 200 mA 300 450 mV I(LDO_OUT) Output current V(LDO_OUT) in regulation 0 280 mA Error-amplifier dc gain 800 V/V V(VIN_LDO) Operating input voltage on VIN_LDO pin Buck regulator is in regulation and supplying at least LDO output plus dropout voltage VDROPOUT 3 20 V Vref2 Voltage reference for FB2 pin V(LDO_OUT) = 1.2 V to 5 V 0.788 0.8 0.812 V ICL(LDO_OUT) Output current limit V(LDO_OUT) = 0 V (LDO_OUT pin is shorted to ground.) 280 1000 mA IQ(LDO) Quiescent current V(VIN) > 9 V, V(EN1) = 0 V, V(EN2) = 5 V, I(LDO_OUT) = 0.01 mA to 0.75 mA, TJ = 25°C 28 75 μA PSRR Power supply ripple rejection V(VIN_LDO)(rip) = 0.5 VPP, I(LDO_OUT) = 200 mA, frequency = 100 Hz, V(LDO_OUT) = 5 V and V(LDO_OUT) = 3.3 V 60 dB PSRR Power supply ripple rejection VVIN_LDO(rip) = 0.5 VPP, I(LDO_OUT) = 200 mA, frequency = 150 kHz, V(LDO_OUT) = 5 V and V(LDO_OUT) = 3.3 V 30 dB Output capacitor ESR = 0.001 Ω to 100 mΩ, large output capacitance may be required for load transient, V(LDO_OUT) ≥ 3.3 V 1 40 μF ESR = 0.001 Ω to 100 mΩ, large output capacitance may be required for load transient, 1.2 V ≤ V(LDO_OUT) < 3.3 V 20 40 μF LDO REGULATOR: RESET (nRST PIN) RESET threshold V(LDO_OUT) decreasing 88% 92% 95% VOH Output high Reset released due to rising LDO_OUT, V(LDO_OUT) ≥ 3.3 V, IOH = 100 µA –5% × V(LDO_OUT) V VOL Output low Reset asserted due to falling LDO_OUT, IOL = 1 mA 0 0.045 0.4 V OVERTEMPERATURE PROTECTION TSD Thermal-shutdown trip point 155 ºC Thys Hysteresis 10 ºC |
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