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TPS56720PWP Datasheet(PDF) 4 Page - Texas Instruments

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No. de pieza TPS56720PWP
Descripción Electrónicos  Synchronous Step-Down Voltage Regulator with Voltage Scaling
Download  44 Pages
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

TPS56720PWP Datasheet(HTML) 4 Page - Texas Instruments

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background image
VBST
SW
SW
VREG5
VOUT
VFB
PGOOD
PGND
PVIN
SDA
GND
PGND
HTSSOP-20
(PowerPAD)
EN
SCL
A0
PVIN
SW
SS
A1
VIN
11
13
12
14
15
16
17
18
19
20
6
5
1
3
2
4
7
8
9
10
4
TPS56C20, TPS56920, TPS56720, TPS56520
SLVSCB6D – NOVEMBER 2013 – REVISED FEBRUARY 2016
www.ti.com
Product Folder Links: TPS56C20 TPS56920 TPS56720 TPS56520
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
6 Pin Configuration and Functions
TPS56520/720/920
20-Pin PWP Package with PowerPAD
(TOP VIEW)
Pin Functions
TERMINAL
I/O
DESCRIPTION
NAME
NUMBER
EN
1
I
Enable. Pull High to enable converter.
SDA
2
I/O
Data I/O terminal.
SCL
3
I/O
Clock I/O terminal.
A1, A0
4,5
I
Chip address.
VIN
6
I
Supply Input for 5.5V linear regulator.
PVIN
7,8
I
Power inputs and connects to high side MOSFET drains.
PGND
9,10
I/O
Ground returns for low-side MOSFETs. Input of current comparator.
SW
11,12,13
I/O
Switch node connections for both the high-side NFETs and low-side NFETs. Input of current
comparator.
VBST
14
I
Supply input for high-side NFET gate drive circuit. Connect 0.1µF ceramic capacitor between
VBST and SW terminals. An internal diode is connected between VREG5 and VBST.
PGOOD
15
O
Open drain power good output. Low means the output voltage of the corresponding output is
out of regulation.
VREG5
16
O
Output of 5.5V linear regulator. Bypass to GND with a high-quality ceramic capacitor of at
least 2.0µF ceramic capacitor. Do not connect any other circuitry to the terminal. VREG5 is
active when EN is H-level.
GND
17
I/O
Signal GND. Connect sensitive SS and VFB returns to GND at a single point.
SS
18
O
Soft-Start Programming terminal. Connect Capacitor from SS terminal to GND to program
Soft-Start time.
VOUT
19
I
Connection to output voltage
VFB
20
I
D-CAP2 feedback input. Connect to output voltage with resistor divider.
Exposed Thermal
Pad
Back side
I/O
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be
connected to GND.


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