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TPS71750QDSERQ1 Datasheet(PDF) 4 Page - Texas Instruments |
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TPS71750QDSERQ1 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 35 page IN N/C (1) EN 6 5 4 OUT GND NR/FB 1 2 3 OUT NR/FB IN GND EN 1 2 3 4 5 IN N/C (1) EN 6 5 4 OUT NR/FB GND 1 2 3 GND 4 TPS717-Q1 SLVSBM4C – SEPTEMBER 2012 – REVISED JANUARY 2016 www.ti.com Product Folder Links: TPS717-Q1 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated 5 Pin Configuration and Functions DCK Package 5-Pin SOT Top View DRV Package 2-mm × 2-mm, 6-Pin WSON Top View DSE Package 1.5-mm × 1.5-mm, 6-Pin WSON Top View (1) N/C = No connection Pin Functions PIN I/O DESCRIPTION NAME NO. DCK (SOT) DRV (WSON) DSE (WSON) EN 3 4 4 I Driving the enable pin (EN) above VEN(high) turns on the regulator. Driving this pin below VEN(low) puts the regulator into standby mode, thereby disabling the output and reducing operating current. FB 4 2 3 I Adjustable voltage version only. The voltage at this pin is fed to the error amplifier. A resistor divider from OUT to FB sets the output voltage when in regulation. GND 2 3 2 — Ground IN 1 6 6 I Input to the device. A 0.1- μF to 1-μF capacitor is recommended for better performance. N/C — 5 5 — Not connected. This pin can be tied to ground to improve thermal dissipation. NR 4 2 3 — Fixed voltage versions only. An external capacitor connected to this pin bypasses noise generated by the internal band gap, thus lowering output noise. OUT 5 1 1 O This pin is the regulated output voltage. A minimum capacitance of 1 μF is required for stability from this pin to ground. |
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