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TPS65150 Datasheet(PDF) 3 Page - Texas Instruments |
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TPS65150 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 47 page  1 2 3 4 5 6 18 17 16 15 14 13 Thermal Pad COMP GD FDLY FB DLY1 DLY2 VGH ADJ CTRL FBP IN VCOM FB DLY1 DLY2 VIN SW SW PGND PGND SUP VCOM IN FBP 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 FDLY GD COMP FBN REF GND DRVN DRVP CPI VGH ADJ CTRL TPS65150 www.ti.com SLVS576B – SEPTEMBER 2005 – REVISED JANUARY 2016 5 Pin Configuration and Functions PWP Package 24-Pin HTSSOP RGE Package Top View 24-Pin VQFN Top View Pin Functions PIN I/O DESCRIPTION NAME VQFN HTSSOP Gate voltage shaping circuit. Connecting a capacitor to this pin sets the fall time ADJ 17 14 I/O of the positive gate voltage V(VGH). This is the compensation pin for the main boost converter. A small capacitor and COMP 1 22 O if required a series resistor is connected to this pin. CPI 19 16 I Input of the VGH isolation switch and gate voltage shaping circuit. Control signal for the gate voltage shaping signal. Apply the control signal for the gate voltage control. Usually the timing controller of the LCD panel generates this signal. If this function is not required, this pin must be connected to VI. By CTRL 16 13 I doing this, the internal switch between CPI and VGH provides isolation for the positive charge pump output V(VGH). DLY2 sets the delay time for V(VGH) to come up. Power-on sequencing adjust. Connecting a capacitor from this pin to ground DLY1 5 2 I/O allows to set the delay time between the boost converter output V(VS) and the negative charge pump V(VGL) during start-up. Power-on sequencing adjust. Connecting a capacitor from this pin to ground allows to set the delay time between the negative charge pump V(VGL) and the DLY2 6 3 I/O positive charge pump during start-up. Note that Q5 in the gate voltage shaping block only turns on when the positive charge pump is within regulation. (This provides input-output isolation of V(VGH)). DRVN 21 18 I/O Negative charge pump driver. DRVP 20 17 I/O Positive charge pump driver. FB 4 1 I Boost converter feedback sense input. FBN 24 21 I Negative charge pump feedback sense input. FBP 15 12 I Positive charge pump feedback sense input. Fault delay. Connecting a capacitor from this pin to VI sets the delay time from the point when one or more of the of the outputs V(VS), V(VGH), V(VGL) drops FDLY 3 24 I/O below its power good threshold until the device shuts down. To restart the device, the input voltage must be cycled to ground. This feature can be disabled by connecting the FDLY pin to VI. Active-low, open-drain output. This output is latched low when the boost GD 2 23 I converter output is in regulation. This signal can be used to drive an external MOSFET to provide isolation for V(VS). GND 22 19 Analog ground. Copyright © 2005–2016, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS65150 |
Número de pieza similar - TPS65150_16 |
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Descripción similar - TPS65150_16 |
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