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TPS7A65xx-Q1 Datasheet(PDF) 3 Page - Texas Instruments |
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TPS7A65xx-Q1 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 19 page GND VOUT VIN 1 2 3 TPS7A6533-Q1, TPS7A6550-Q1 www.ti.com SLVSA98D – MAY 2010 – REVISED DECEMBER 2015 5 Pin Configuration and Functions KVU Package 3-Pin TO-252 Top View Pin Functions PIN I/O DESCRIPTION NO. NAME Input voltage pin: The unregulated input voltage is supplied to this pin. A bypass capacitor is connected 1 VIN I between VIN pin and GND pin to dampen input line transients. 2 GND I/O Ground pin: This is signal ground pin of the IC. Regulated output voltage pin: This is a regulated voltage output (VOUT = 3.3 V or 5 V, as applicable) pin 3 VOUT O with a limitation on maximum output current. To achieve stable operation and prevent oscillation, an external output capacitor (COUT) with low ESR is connected between this pin and the GND pin. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS7A6533-Q1 TPS7A6550-Q1 |
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