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TPS62510DRCRG4 Datasheet(PDF) 8 Page - Texas Instruments |
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TPS62510DRCRG4 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 28 page SW MOSFETDriver AntiShootThrough ConverterControl Logic HighSide Current Sense LowSide Current Sense Vref 0.6V Vref 0.6V 1.5MHz SawTooth Summing Comparator FB Loop Compensation Error Amplifier PFM Comparator Analog Softstart PLL MODE PVIN Bandgap Undervoltage Lockout ThermalShutdown AVIN PGND AGND 0.6V PG OVT EN EN OutputVoltage Tracking R1 R2 (SeeNote A) Vref -2% PFM/PWM Transition Q1 Q2 Q3 Q4 R3 R4 VOUT Generator 0.6V Vref 0.6V TPS62510 SLVS651B – MAY 2006 – REVISED DECEMBER 2015 www.ti.com 7.2 Functional Block Diagram A. R1 and R2 are only used for the fixed output voltage version. 7.3 Feature Description 7.3.1 Output Voltage Tracking (OVT) In applications where a processor or FPGA is powered, it is important that the I/O voltage and core voltage start- up in a controlled way to avoid possible processor and FPGA latch-up. To implement this, the TPS62510 has an output voltage tracking feature where the internal reference voltage for the error amplifier follows the voltage applied to OVT, until OVT reaches Vref. Vref is the nominal internal reference voltage, typically 0.6 V. Figure 7 shows a typical application where an external voltage (V1) is applied to OVT pin using a resistor divider. 8 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: TPS62510 |
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