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TPS92691QPWPRQ1 Datasheet(PDF) 5 Page - Texas Instruments |
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TPS92691QPWPRQ1 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 46 page TPS92691, TPS92691-Q1 www.ti.com SLVSD68 – DECEMBER 2015 6.4 Thermal Information TPS92691/-Q1 THERMAL METRIC(1) PWP (HTSSOP) UNIT 16 PINS RθJA Junction-to-ambient thermal resistance 40.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 26.1 °C/W RθJB Junction-to-board thermal resistance 22.2 °C/W ψJT Junction-to-top characterization parameter 0.8 °C/W ψJB Junction-to-board characterization parameter 22.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.3 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics TJ = –40°C to 140°C, VIN = 14 V, VIADJ = 2.2 V, CVCC = 1 µF, CCOMP = 2.2 nF, RCS = 100 mΩ, RT = 20 kΩ, VPWM = 5 V, no load on GATE and DDRV (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT VOLTAGE (VIN) VDO LDO dropout voltage ICC = 20 mA, VIN = 5 V 300 mV BIAS SUPPLY (VCC) VCC(REG) Regulation voltage No load 7.0 7.5 8.0 V VCC rising threshold, VIN = 8 V 4.1 4.35 V VCC(UVLO) Supply undervoltage protection VCC falling threshold, VIN = 8 V 3.75 4.0 V Hysteresis 100 mV ICC(LIMIT) Supply current limit VCC = 0 V 26 38 46 mA ICC(STBY) Supply stand-by current VPWM = 0 V 1.8 2.1 mA ICC(SW) Supply switching current VCC = 7.5 V, CGATE = 1 nF 5.1 6.6 mA OSCILLATOR (RT/SYNC) RT = 40 kΩ 165 200 230 kHz ƒSW Switching frequency RT = 20 kΩ 327 390 448 kHz VRT RT output voltage 1 V SYNC rising threshold VRT/SYNC rising 2.7 3.1 V VSYNC SYNC falling threshold VRT/SYNC falling 1.8 2 V tSYNC(MIN) Minimum SYNC clock pulse width 100 ns GATE DRIVER (GATE) RGH Gate driver high side resistance IGATE = –10 mA 5.4 11.2 Ω RGL Gate driver low side resistance IGATE = 10 mA 4.3 10.5 Ω CURRENT SENSE (IS) VIS(LIMIT) Current limit threshold 497 525 550 mV tIS(BLANK) Leading edge blanking time 103 150 188 ns tIS(FAULT) Current limit fault time 35 µs tILMT(DLY) IS to GATE propagation delay VIS pulsed from 0 to 1 V 100 ns PWM COMPARATOR AND SLOPE COMPENSATION DMAX Maximum duty cycle 90.4% 93% 94.7% VLV IS to COMP level shift voltage No slope compensation added 1.17 1.5 1.8 V D = DMAX (with max slope VSL Slope compensation 200 mV compensation) ILV IS level shift bias current No slope compensation added 25 µA (1) All voltages are with respect to AGND unless otherwise noted Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPS92691 TPS92691-Q1 |
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