GND

1

VBST

6

SW

2

EN

5

VIN

3

VFB

4

TPS563201, TPS563208

www.ti.com

SLVSD90 – DECEMBER 2015

5 Pin Configuration and Functions

DDC Package

6-Pin SOT

Top View

Pin Functions

PIN

I/O

DESCRIPTION

NAME

NO.

Ground pin Source terminal of low-side power NFET as well as the ground terminal for

GND

1

—

controller circuit. Connect sensitive VFB to this GND at a single point.

SW

2

O

Switch node connection between high-side NFET and low-side NFET.

VIN

3

I

Input voltage supply pin. The drain terminal of high-side power NFET.

VFB

4

I

Converter feedback input. Connect to output voltage with feedback resistor divider.

EN

5

I

Enable input control. Active high and must be pulled up to enable the device.

Supply input for the high-side NFET gate drive circuit. Connect 0.1 µF capacitor between

VBST

6

O

VBST and SW pins.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

VIN, EN

–0.3

19

V

VBST

–0.3

25

V

VBST (10 ns transient)

–0.3

27

V

Input voltage

VBST (vs SW)

–0.3

6.5

V

VFB

–0.3

6.5

V

SW

–2

19

V

SW (10 ns transient)

–3.5

21

V

–40

150

°C

–55

150

°C

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

±3000

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

±1500

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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