Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
ADC0811CCV Datasheet(PDF) 10 Page - National Semiconductor (TI) |
|
|
ADC0811CCV Datasheet(HTML) 10 Page - National Semiconductor (TI) |
10 / 14 page Functional Description (Continued) at least 64 w2 clocks to insure that the AD has completed its conversion If SCLK is enabled sooner synchronizing to the data output on DO is not possible since an end of con- version signal from the AD is not available and the actual conversion time is not known With CS low during the con- version time (64 w2 max) DO will go low after the eighth falling edge of SCLK and remain low until the conversion is completed Once the conversion is through DO will transmit the MSB The rest of the data will be shifted out once SCLK is enabled as discussed previously If CS goes high during the conversion sequence DO is tri- stated and the result is not affected so long as CS remains high until the end of the conversion 12 MULTIPLEXER ADDRESSING The four bit mux address is shifted MSB first into DI Input data corresponds to the channel selected as shown in table 1 Care should be taken not to send an address greater than or equal to twelve (11XX) as this puts the AD in a digital testing mode In this mode the analog inputs CH0 thru CH3 become digital outputs for our use in production testing 20 ANALOG INPUT 21 THE INPUT SAMPLE AND HOLD The ADC0811’s samplehold capacitor is implemented in its capacitive ladder structure After the channel address is re- ceived the ladder is switched to sample the proper analog input This sampling mode is maintained for 1 msec after the eighth SCLK falling edge The hold mode is initiated with the start of the conversion process An acquisition window of 4tSCLKa1 msec is therefore available to allow the ladder capacitance to settle to the analog input voltage Any change in the analog voltage before or after the acquisition window will not effect the AD conversion result In the most simple case the ladder’s acquisition time is de- termined by the Ron (3K) of the multiplexer switches and the total ladder capacitance (90pf) These values yield an acqui- sition time of about 2 msec for a full scale reading There- fore the analog input must be stable for at least 2 msec before and 1 msec after the eighth SCLK falling edge to ensure a proper conversion External input source resist- ance and capacitance will lengthen the acquisition time and should be accounted for Other conventional sample and hold error specifications are included in the error and timing specs of the AD The hold step and gain error samplehold specs are taken into ac- count in the ADC0811’s total unadjusted error while the hold settling time is included in the AD’s max conversion time of 64 w2 clock periods The hold droop rate can be thought of as being zero since an unlimited amount of time can pass between a conversion and the reading of data However once the data is read it is lost and another conver- sion is started Typical Applications ADC0811-INS8048 INTERFACE TLH5587 – 21 10 |
Número de pieza similar - ADC0811CCV |
|
Descripción similar - ADC0811CCV |
|
|
Enlace URL |
Política de Privacidad |
ALLDATASHEET.ES |
¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |