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TPS650731RSLR Datasheet(PDF) 7 Page - Texas Instruments |
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TPS650731RSLR Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 98 page  TPS65070, TPS65072 TPS65073, TPS650731, TPS650732 www.ti.com SLVS950H – JULY 2009 – REVISED SEPTEMBER 2015 Pin Functions (continued) PIN NO. I/O DESCRIPTION NAME TPS65072 TPS6507x VDCDC3 29 29 I Feedback voltage sense input, connect directly to Vout3 VINDCDC1/2 21 21 I Input voltage for DCDC1 and DCDC2 step-down converter. This pin must be connected to the SYS pin. VINLDO1/2 3 3 I Input voltage for LDO1 and LDO2 VIN_DCDC3 32 32 I Input voltage for DCDC3 step-down converter. This pin must be connected to the SYS pin. VLDO1 4 4 O Output voltage of LDO1 VLDO2 2 2 O Output voltage of LDO2 Thermal Pad — Power ground connection for the PMU. Connect to GND 8 Specifications 8.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT On all pins except the pins listed below with respect to AGND –0.3 7 On pins INT, RESET, PGOOD, PB_OUT with respect to AGND –0.3 V(AVDD6) On pins VINDCDC1/2, VINDCDC3, VINLDO respect to AGND –0.3 V(SYS) Voltage V On pins AD_IN1, AD_IN2, AD_IN3, AD_IN4 with respect to AGND –0.3 3.3 On pins ISINK1, ISINK2, AC, USB –0.3 20 On pin L4 (output voltage of boost converter), FB_wLED –0.3 40 In/Out at SYS, AC, USB, BAT, L3 3000 mA Current In/Out at all other pins 1000 mA Power Continuous total power dissipation See Dissipation Ratings(2) Operating free-air temperature, TA 40 85 °C Temperature Maximum junction temperature, TJ 125 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The thermal resistance RθJP junction to thermal pad of the RSL package is 1.1 K/W. The value for RθJA was measured on a high K board. 8.2 ESD Ratings VALUE UNIT Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V(ESD) Electrostatic discharge V Charged device model (CDM), per JEDEC specification JESD22-C101, ±500 all pins(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 8.3 Recommended Operating Conditions MIN NOM MAX UNIT BATTERY CHARGER AND POWER PATH VIN Input voltage for power path manager at pins AC or USB 4.3 17 Input voltage for power path manager at pins AC or USB, charger and power path 4.3 5.8 active (no overvoltage lockout) V Input voltage for power path manager at pins AC or USB in case there is no battery 3.6 17 connected at pin BAT IIN Input current at AC pin 2.5 A Input current at USB pin 1.3 Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TPS65070 TPS65072 TPS65073 TPS650731 TPS650732 |
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