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ADC08L060CIMT Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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ADC08L060CIMT Datasheet(HTML) 5 Page - National Semiconductor (TI) |
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5 / 19 page  Converter Electrical Characteristics (Continued) The following specifications apply for V A =VDR = +3.0VDC,VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50% duty cycle. Boldface limits apply for T A =TMIN to TMAX: all other limits TA = 25˚C (Notes 7, 8) Symbol Parameter Conditions Typical (Note 9) Limits (Note 9) Units (Limits) V OH High Level Output Voltage V A =VDR = 2.7V, IOH = −400 µA 2.6 2.4 V (min) V OL Low Level Output Voltage V A =VDR = 2.7V, IOL = 1.0 mA 0.4 0.5 V (max) DYNAMIC PERFORMANCE ENOB Effective Number of Bits f IN = 10.1 MHz, VIN = FS − 0.25 dB 7.6 6.9 Bits f IN = 29 MHz, VIN = FS − 0.25 dB 7.4 Bits (min) SINAD Signal-to-Noise & Distortion f IN = 10.1 MHz, VIN = FS − 0.25 dB 47.4 43.3 dB f IN = 29 MHz, VIN = FS − 0.25 dB 46.1 dB (min) SNR Signal-to-Noise Ratio f IN = 10.1 MHz, VIN = FS − 0.25 dB 48 44.5 dB f IN = 29 MHz, VIN = FS − 0.25 dB 47.2 dB (min) SFDR Spurious Free Dynamic Range f IN = 10.1 MHz, VIN = FS − 0.25 dB 59.1 dBc f IN = 29 MHz, VIN = FS − 0.25 dB 54.5 dBc THD Total Harmonic Distortion f IN = 10.1 MHz, VIN = FS − 0.25 dB −56.9 dBc f IN = 29 MHz, VIN = FS − 0.25 dB −53.3 dBc HD2 2nd Harmonic Distortion f IN = 10.1 MHz, VIN = FS − 0.25 dB -61.1 dBc f IN = 29 MHz, VIN = FS − 0.25 dB −54.9 dBc HD3 3rd Harmonic Distortion f IN = 10.1 MHz, VIN = FS − 0.25 dB −64.2 dBc f IN = 29 MHz, VIN = FS − 0.25 dB −63.1 dBc IMD Intermodulation Distortion f 1 = 11 MHz, VIN = FS − 6.25 dB f 2 = 12 MHz, VIN = FS − 6.25 dB −55 dBc POWER SUPPLY CHARACTERISTICS I A Analog Supply Current DC Input 13 15.9 mA (max) f IN = 10 MHz, VIN =FS−3dB 14 mA DRI D Output Driver Supply Current DC Input 0.04 0.2 mA (max) f IN = 10 MHz, VIN =FS−3dB 4.2 mA I A + DRI D Total Operating Current DC Input 13 16.1 mA (max) f IN = 10 MHz, VIN = FS − 3 dB, PD = Low 18.2 CLK Low, PD = Hi 0.33 PC Power Consumption DC Input 39 48.3 mW (max) f IN = 10 MHz, VIN = FS − 3 dB, PD = Low 53 mW CLK Low, PD = Hi 0.3 mW PSRR 1 Power Supply Rejection Ratio FSE change with 2.7V to 3.3V change in V A −51 dB PSRR 2 Power Supply Rejection Ratio SNR with 200 mW at 1MHz on supply 45 dB AC ELECTRICAL CHARACTERISTICS f C1 Maximum Conversion Rate 80 60 MHz (min) f C2 Minimum Conversion Rate 10 MHz t CL Minimum Clock Low Time 0.62 ns (min) t CH Minimum Clock High Time 0.62 ns (min) DC Clock Duty Cycle 5 95 %(min) %(max) t OH Output Hold Time CLK to Data Invalid 5.2 ns t OD Output Delay CLK to Data Transition 7.1 5.0 ns (min) 9.4 ns (max) Pipeline Delay (Latency) 5 Clock Cycles t AD Sampling (Aperture) Delay CLK Rise to Acquisition of Data 2.6 ns www.national.com 5 |
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