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PI3HDMI301 Datasheet(PDF) 4 Page - Pericom Semiconductor Corporation

No. de Pieza. PI3HDMI301
Descripción  3:1 Active Switch for HDMI Signals with Optimized Equalization for Enhanced Signal Integrity
Descarga  16 Pages
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Fabricante  PERICOM [Pericom Semiconductor Corporation]
Página de inicio  http://www.pericom.com
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PI3HDMI301 Datasheet(HTML) 4 Page - Pericom Semiconductor Corporation

 
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4
PS8959B
10/01/09
PI3HDMI301
3:1 Active Switch for HDMI™ Signals with
Optimized Equalization for Enhanced Signal Integrity
ADVANCE INFORMATION - COMPANY CONFIDENTIAL
All trademarks are property of their respective owners.
Pin Description
80 LQFP Pin #
64 TQFN Pin #
Pin Name
I/O
Description
9, 12, 15, 6
7, 9,12, 4
D0+1, D1+1, D2+1, CLK+1
I
Port 1 TMDS Positive inputs
71, 74, 77, 68
57, 59, 62, 54
D0+2, D1+2, D2+2, CLK+2
I
Port 2 TMDS Positive inputs
52, 55, 58, 49
43, 45, 48, 40
D0+3, D1+3, D2+3, CLK+3
I
Port 3 TMDS Positive inputs
8, 11, 14, 5
6, 8, 11, 3
D0-1, D1-1, D2-1, CLK-1
I
Port 1 TMDS Negative inputs
70, 73, 76, 67
56, 58, 61, 53
D0-2, D1-2, D2-2, CLK-2
I
Port 2 TMDS Negative inputs
51, 54, 57, 48
42, 44, 47, 39
D0-3, D1-3, D2-3, CLK-3
I
Port 3 TMDS Negative inputs
4, 10, 16, 24, 30,
36, 37, 47, 53, 59,
65, 66, 72, 78
GND
Ground
80
63
HPD1
O
Port 1 HPD output
62
50
HPD2
O
Port 2 HPD output
44
36
HPD3
O
Port 3 HPD output
40
32
HPD_Sink
I
Sink side hot plug detector input. High: 5-V
power signal asserted from source to sink
and EDID is ready.
Low: No 5-V power signal asserted from
source to sink, or EDID is not ready.
42
34
OE
I
Output Enable, Active LOW
3
2
SCL1
I/O
Port 1 DDC Clock
64
52
SCL2
I/O
Port 2 DDC Clock
46
38
SCL3
I/O
Port 3 DDC Clock
38
31
SCL_Sink
I/O
Sink Side DDC Clock
2
1
SDA1
I/O
Port 1 DDC Data
63
51
SDA2
I/O
Port 2 DDC Data
45
37
SDA3
I/O
Port 3 DDC Data
39
31
SDA_Sink
I/O
Sink Side DDC Data
21, 22, 23
17, 18, 19
S1, S2, S3
I
Source Input Control
7, 13, 17, 27, 33,
43, 50, 56, 61, 69,
75, 79
5, 10, 22, 27, 35,
41, 46, 55, 60
VDD
3.3V Power Supply
31, 28, 25, 34
25, 23, 20, 28
D0+, D1+, D2+, CLK+
O
TMDS positive outputs
32, 29, 26, 35
26, 24, 21, 29
D0-, D1-, D2-, CLK-
O
TMDS negative outputs
41, 60
33, 49
EQ_S0, EQ_S1
I
Equalizer controls, both controls have
internal pull-ups
19, 18, 20, 1
15, 14, 16, 64
OC_S0, OC_S1,
OC_S2, OC_S3
I
Output buffer controls, all control bits have
internal pull-ups
09-0054


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